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与X84161 X641 X129 MPS EEPROM 接
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2009-05-26
mintsy
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The following C routines can be used for interfacing to an MPS E2PROM and can be easily adapted for many different hardware platforms. For debugging purposes,a PC was used in conjunction with the XK84 ISA interface card. The schematic for this ISA card is shown in Figure 1. Depending on the position of
jumpers J1 and J2, an MPS E2PROM is memorymapped into 1 of 4 I/O address banks (as determined by jumper J2). Jumper J1 determines the exact address within the bank. This allows for any address to be chosen in the following ranges: 301h-307h, 309h-30Fh, 311h-317h, or 319h-31Fh. The single unused address in the selected bank (i.e. 300h, 308h, 310h, or 318h) is reserved for a D flip-flop used to toggle the WP pin. This glue logic is only necessary to provide a
generic ISA bus interface for an MPS E2PROM. For such applications, much of this logic may already exist on the target PC card or can be eliminated with a user supplied CE strobe (i.e. jumper J3).
jumpers J1 and J2, an MPS E2PROM is memorymapped into 1 of 4 I/O address banks (as determined by jumper J2). Jumper J1 determines the exact address within the bank. This allows for any address to be chosen in the following ranges: 301h-307h, 309h-30Fh, 311h-317h, or 319h-31Fh. The single unused address in the selected bank (i.e. 300h, 308h, 310h, or 318h) is reserved for a D flip-flop used to toggle the WP pin. This glue logic is only necessary to provide a
generic ISA bus interface for an MPS E2PROM. For such applications, much of this logic may already exist on the target PC card or can be eliminated with a user supplied CE strobe (i.e. jumper J3).
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