应用电子电路
JTAG Header Pin | JTAG Cable Function | MAXQ2000 JTAG Master Connection |
MAXQ2000 JTAG Slave Connection |
1 | TCK (Test Clock) | P0.0 (Output) | P4.0 (Input) |
2 | GND | GND | GND |
3 | TDO (Test Data Out) | P0.1 (Input) | P4.3 (Output) |
4 | VREF | – | – |
5 | TMS (Test Mode Select) | P0.2 (Output) | P4.2 (Input) |
6 | nRESET | P0.4 (Open Drain) | nRESET (Input) |
7 | Keyed pin | – | – |
8 | +5V | – | – |
9 | TDI (Test Data In) | P0.3 (Output) | P4.1 (Input) |
10 | GND | GND | GND |
Board | Switch or Jumper | Setting | Notes |
Serial-to-JTAG Board | JH1 | Connected | |
JH2 | Connected | ||
JH3 | Connected | Supplies 5V power over JTAG cable | |
Master MAXQ2000 EV Kit | JU1 | Pins 1 and 2 connected | Powers VDD from 2.5V supply |
JU2 | Pins 1 and 2 connected | Powers VDDIO from 3.6V supply | |
JU3 | Pins 1 and 2 connected | Powers VLCD from 3.6V supply | |
JU11 | Connected | Powers kit board from JTAG 5V supply | |
DIP SW1 | Switches #4 and #8 ON; all other switches OFF | Enables serial port 0 output to J5 | |
DIP SW3 | All switches OFF | ||
DIP SW6 | All switches OFF | ||
Slave MAXQ2000 EV Kit | JU1 | Pins 1 and 2 connected | Powers VDD from 2.5V supply |
JU2 | Pins 1 and 2 connected | Powers VDDIO from 3.6V supply | |
JU3 | Pins 1 and 2 connected | Powers VLCD from 3.6V supply | |
DIP SW1 | All switches OFF | ||
DIP SW3 | All switches OFF | ||
DIP SW6 | All switches OFF |
JTAG Signal | Signal Name | Direction (Master) | Direction (Slave) | Signal Description |
TMS | Test Mode Select | Output | Input | This signal line, along with the TCK line, is used to shift the TAP controller from one operational state to the next. |
TCK | Test Clock | Output | Input | This signal provides the clock for the JTAG interface. The JTAG clock is limited to a maximum of the slave's clock frequency divided by 8. For example, if the slave is running at a clock frequency of 8MHz, the JTAG clock at TCK cannot run any faster than 1MHz. |
TDI | Test Data In | Output | Input | This signal carries data that is sent from the master to the slave. |
TDO | Test Data Out | Input | Output | This signal carries data that is sent from the slave back to the master. |
#define TCK PO0.0 ; Test Clock - Master output #define TDO PI0.1 ; Test Data Out - Slave output, master input #define TMS PO0.2 ; Test Mode Sel - Master output #define TDI PO0.3 ; Test Data In - Master output #define RST PD0.4 ; Reset - Master open-drain output (on 1)四条JTAG线工作在标准驱动模式下。从主机角度看,TMS、TCK和TDI总是被驱动为输出,而TDO (由从机驱动)总是为输入。JTAG线的方向固定,不是双向的。nRESET线是特殊情况,被配置为主机侧开漏输出。通常,从机将自己的nRESET线拉至高电平,因此,主机只能将该线拉低(复位从机时),或者完全释放它(在其他所有时间)。主机不应将从机的nRESET线驱动为高电平。
;============================================================================== ;= ;= initializeJTAG ;= ;= Sets up the port pins for the JTAG interface. ;= ;= Inputs : None ;= Outputs : None ;= Destroys : None ;= initializeJTAG: move PD0.0, #1 ; TCK - master output move PO0.0, #1 ; Drive high move PD0.1, #0 ; TDO - master input move PO0.1, #1 ; Weak pullup on move PD0.2, #1 ; TMS - master output move PO0.2, #1 ; Drive low move PD0.3, #1 ; TDI - master output move PO0.3, #1 ; Drive high move PD0.4, #0 ; RST - open drain when 1, tristate when 0 move PO0.4, #0 ; Weak pullup off ret端口引脚初始化之后,采用例程clock0和clock1来同步TMS线上的静态0和1,使TAP控制器从一个状态转换到另一状态。只要JTAG时钟速率保持低于从机微控制器系统时钟速率1/8的最大值,JTAG时钟可以采用任何频率。这里不需要考虑主机的系统时钟速率;它不需要和从机系统时钟速率相匹配。主机可以比从机运行的快或者慢,而不会导致出现JTAG通信问题。
#define JCLOCK 40 ; 100kHz : (((10us / (1/8MHz)) / 2) ;============================================================================== ;= ;= clock0 ;= ;= Clocks a zero TMS bit into the JTAG interface. ;= ;= Inputs : None ;= Outputs : None ;= Destroys : LC[0] clock0: move TMS, #0 ; Drive TMS low move LC[0], #JCLOCK djnz LC[0], $ move TCK, #1 ; Clock rising edge move LC[0], #JCLOCK djnz LC[0], $ move TCK, #0 ; Clock falling edge move LC[0], #JCLOCK djnz LC[0], $ ret ;============================================================================== ;= ;= clock1 ;= ;= Clocks a one TMS bit into the JTAG interface. ;= ;= Inputs : None ;= Outputs : None ;= Destroys : LC[0] clock1: move TMS, #1 ; Drive TMS high move LC[0], #JCLOCK djnz LC[0], $ move TCK, #1 ; Clock rising edge move LC[0], #JCLOCK djnz LC[0], $ move TCK, #0 ; Clock falling edge move LC[0], #JCLOCK djnz LC[0], $ ret利用这两个例程,我们可以增加另一个例程来初始化TAP控制器,迫使它回到Test-Logic-Reset状态。注意Test-Logic-Reset状态,正如其名称的含义,它对TAP逻辑进行彻底复位,包括确定启动加载程序是否使能以及启动加载程序使用哪一接口位(SPE和PSS[1:0])。因此,一旦进入启动加载程序模式,设置TAP控制器为Test-Logic-Reset,对器件进行复位,退出启动加载程序模式。演示应用程序中使用的JTAG例程(除了testLogicReset本身之外)都假定TAP控制器在例程启动时处于Run-Test-Idle状态。在JTAG通信期间,TAP控制器在不同状态间转换;例程最后,TAP控制器总是返回到Run-Test-Idle。
;============================================================================== ;= ;= testLogicReset ;= clock0, clock1 ;= ;= Resets the JTAG/TAP controller to its starting state. ;= ;= Inputs : None ;= Outputs : None ;= Destroys : LC[0] ;= testLogicReset: call clock1 call clock1 call clock1 call clock1 call clock1 call clock1 call clock1 call clock0 ; Brings us to Run-Test-Idle ret
;============================================================================== ;= ;= shift ;= ;= In a shift register state, clocks in a TDI bit and clocks out a TDO bit. ;= ;= Inputs : C - Bit to shift in to TDI. ;= Outputs : C - Bit shifted out from TDO. ;= Destroys : PSW, LC[0] ;= shift: jump C, shift_bit1 shift_bit0: move TDI, #0 ; Shift in zero bit jump shift_bitEnd shift_bit1: move TDI, #1 ; Shift in one bit jump shift_bitEnd shift_bitEnd: move LC[0], #JCLOCK djnz LC[0], $ move TCK, #1 ; Rising edge, TDI is sampled move LC[0], #JCLOCK djnz LC[0], $ move TCK, #0 ; Falling edge, TDO is driven out move LC[0], #JCLOCK djnz LC[0], $ move C, TDO ; Latch TDO value ret对于传送的每一位,除了最后一位之外,TMS必须保持低电平。这非常重要,因为当每一位移入和移出时,状态机保持在Shift-IR或者Shift-DR状态。在最后一个比特周期,TMS必须被驱动为高电平,这样,随着最后一位的输入和输出,TAP控制器将进入Exit1-DR或者Exit1-IR状态。
TCK | TMS | TDI | TDO | TAP State | Shift Register | Instruction Register | ||||
bit 2 | bit 1 | bit 0 | bit 2 | bit 1 | bit 0 | |||||
0 | 1 | x | x | Run-Test-Idle | x | x | x | 0 | 1 | 1 |
1 | 1 | x | x | Select-DR-Scan | x | x | x | 0 | 1 | 1 |
0 | 1 | x | x | Select-DR-Scan | x | x | x | 0 | 1 | 1 |
1 | 1 | x | x | Select-IR-Scan | x | x | x | 0 | 1 | 1 |
0 | 0 | x | x | Select-IR-Scan | x | x | x | 0 | 1 | 1 |
1 | 0 | x | x | Capture-IR | 0 | 0 | 1 | 0 | 1 | 1 |
0 | 0 | x | x | Capture-IR | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | x | x | Shift-IR | 0 | 0 | 1 | 0 | 1 | 1 |
0 | 0 | 0 | x | Shift-IR | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | 0 | x | Shift-IR | 0 | 0 | 1 | 0 | 1 | 1 |
0 | 0 | 0 | 1 | Shift-IR | 0 | 0 | 0 | 0 | 1 | 1 |
1 | 0 | 0 | 1 | Shift-IR | 0 | 0 | 0 | 0 | 1 | 1 |
0 | 1 | 1 | 0 | Shift-IR | 0 | 0 | 0 | 0 | 1 | 1 |
1 | 1 | 1 | 0 | Exit1-IR | 0 | 0 | 0 | 0 | 1 | 1 |
0 | 1 | x | 0 | Exit1-IR | 1 | 0 | 0 | 0 | 1 | 1 |
1 | 1 | x | 0 | Update-IR | 1 | 0 | 0 | 1 | 0 | 0 |
0 | 0 | x | x | Update-IR | 1 | 0 | 0 | 1 | 0 | 0 |
1 | 0 | x | x | Run-Test-Idle | x | x | x | 1 | 0 | 0 |
;============================================================================== ;= ;= shiftIR3 ;= clock0, clock1, shift ;= ;= Shifts a 3-bit value into the IR register. ;= ;= Inputs : A[0] - Low three bits contain value to shift into IR ;= Outputs : None ;= Destroys : AP, APC, A[0], PSW, LC[0] ;= shiftIR3: move APC, #80h ; Acc => A[0], turn off auto inc/dec call clock1 ; (Select DR Scan) call clock1 ; (Select IR Scan) call clock0 ; (Capture IR - loads 001b to shift register) call clock0 ; (Shift IR) move TMS, #0 ; Drive TMS low move C, TDO ; xxxxx210 c = s rrc ; sxxxxx21 c = 0 call shift ; Shift in IR bit 0 rrc ; ssxxxxx2 c = 1 call shift ; Shift in IR bit 1 rrc ; sssxxxxx c = 2 move TMS, #1 ; Drive TMS high for last bit call shift ; Shift in IR bit 2 (Exit1 IR) call clock1 ; (Update IR) call clock0 ; (Run Test Idle) ret
;============================================================================== ;= ;= shiftDR3 ;= ;= Shifts a 3-bit value into the DR register. This operation should only be ;= performed when IR =100b (System Programming Mode). ;= ;= Inputs : A[0] - Low 3 bits contain value to shift into SPB (PSS1:PSS0:SPE) ;= Outputs : None ;= Destroys : AP, APC, A[0], PSW, LC[0] shiftDR3: move APC, #80h ; Acc => A[0], turn off auto inc/dec call clock1 ; (Select DR Scan) call clock0 ; (Capture DR) call clock0 ; (Shift DR) move TMS, #0 ; Drive TMS low move C, TDO ; xxxxx210 c = s rrc ; sxxxxx21 c = 0 call shift ; Shift in DR bit 0 rrc ; ssxxxxx2 c = 1 call shift ; Shift in DR bit 1 rrc ; sssxxxxx c = 2 move TMS, #1 ; Drive TMS high for last bit call shift ; Shift in DR bit 2 (Exit1 DR) call clock1 ; (Update DR) call clock0 ; (Run Test Idle) ret ;============================================================================== ;= ;= shiftDR ;= clock0, clock1, shift ;= ;= Shifts a 10-bit value into and out of the DR register. This operation ;= should only be performed when IR = 010b (Debug/Loader Mode). ;= ;= Inputs : A[0] - Byte value (input) to shift into DR ;= Outputs : A[0] - Byte value (output) shifted out of DR ;= A[1] - Low two bits are status bits 1:0 shifted out of DR ;= A[15] - Byte value shifted in, cached for use by shiftDR_next ;= Destroys : AP, APC, PSW, LC[0] shiftDR: move APC, #80h ; Acc => A[0], turn off auto inc/dec move A[15], A[0] ; Cache input byte value for use by shiftDR_next sla2 ; Add two empty bits (for status) call clock1 ; (Select DR Scan) call clock0 ; (Capture DR) call clock0 ; (Shift DR) move TMS, #0 ; Drive TMS low move C, TDO ; xxxxxxxx76543210 c = s rrc call shift ; Shift in DR bit 0 rrc call shift ; Shift in DR bit 1 rrc call shift ; Shift in DR bit 2 rrc call shift ; Shift in DR bit 3 rrc call shift ; Shift in DR bit 4 rrc call shift ; Shift in DR bit 5 rrc call shift ; Shift in DR bit 6 rrc call shift ; Shift in DR bit 7 rrc call shift ; Shift in DR bit 8 rrc move TMS, #1 ; Drive TMS high for last bit call shift ; Shift in DR bit 9 (Exit1 DR) call clock1 ; (Update DR) call clock0 ; (Run Test Idle) push Acc ; sddd dddd 10xx xxxx sra4 ; ssss sddd dddd 10xx sra2 ; ssss sssd dddd dd10 and #0003h ; ---- ---- ---- --10 move A[1], Acc ; Return status bits only in A[1] pop Acc and #0FF00h xch ; Return data bits only in A[0] ret
#define IR_DEBUG 010b ; Debug Mode #define IR_BYPASS 011b ; Bypass Mode (default) #define IR_SYSTEM_PROG 100b ; System Programming Mode (activate loader) ; System Programming Register settings #define SP_EXECUTE 000b ; Bootloader disabled #define SP_LOAD_JTAG 001b ; Activate JTAG bootloader #define SP_LOAD_UART 011b ; Activate UART bootloader #define SP_LOAD_SPI 101b ; Activate SPI bootloader (invalid on 2000) #define SP_RESERVED 111b ; Reserved value ... call initializeJTAG ; Set up port pins for JTAG call testLogicReset ; Reset JTAG port (ending state: Run-Test-Idle) move Acc, #IR_SYSTEM_PROG call shiftIR3 ; Load the System Programming instruction into IR move Acc, #SP_LOAD_JTAG call shiftDR3 ; Enable the bootloader in JTAG interface mode move RST, #1 ; Drive nRESET low move Acc, #100 ; Delay for 100ms call delayMS call clock0 ; Remain in Run-Test-Idle move RST, #0 ; Release nRESET move Acc, #100 ; Delay for 100ms call delayMS move Acc, #IR_DEBUG call shiftIR3 ; Enable access to the 10-bit debug shift register ;;;; Bootloader commands may now be shifted through the DR register call waitForPrompt ; Verify that the bootloader is responding ...
;============================================================================== ;= ;= sendCommand ;= ;= Transmits a loader command by shifting bytes through DR. ;= ;= Inputs : DP[0] - Points to area of RAM which stores input bytes ;= for command and which will be filled with output. ;= LC[1] - Number of bytes to transmit/receive ;= Outputs : C - Set on JTAG communication error ;= Destroys : AP, APC, A[0], A[1], A[2], A[15], PSW, LC[0] ;= sendCommand: move APC, #80h ; Acc => A[0], turn off auto inc/dec push LC[1] call waitForPrompt pop LC[1] jump C, sendCommand_fail move Acc, @DP[0] ; Read first byte to transmit call shiftDR push Acc move Acc, A[1] cmp #3 ; Should be valid status since we had a prompt pop Acc jump NE, sendCommand_fail move @DP[0], Acc ; Store first received byte move NUL, @DP[0]++ ; Increment data pointer djnz LC[1], sendCommand_loop jump sendCommand_pass sendCommand_loop: move A[2], #10 ; Number of retries allowed sendCommand_retry: move Acc, @DP[0] ; Get next byte to transmit call shiftDR_next push Acc move Acc, A[1] cmp #3 pop Acc jump NE, sendCommand_stall move @DP[0], Acc ; Store received byte move NUL, @DP[0]++ ; Increment data pointer djnz LC[1], sendCommand_loop jump sendCommand_pass sendCommand_stall: move LC[0], #8000 ; About a millisecond djnz LC[0], $ move Acc, A[2] sub #1 jump NZ, sendCommand_retry jump sendCommand_fail
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Code | Family/Command |
0 | 0 | 0 | 0 | x | x | x | x | 0 x h | Family 0—Informational Commands |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 00h | No Operation |
0 | 0 | 0 | 1 | 01h | Exit Loader | ||||
0 | 0 | 1 | 0 | 02h | Master Erase | ||||
0 | 0 | 1 | 1 | 03h | Password Match | ||||
0 | 1 | 0 | 0 | 04h | Get Status | ||||
0 | 1 | 0 | 1 | 05h | Get Supported Commands | ||||
0 | 1 | 1 | 0 | 06h | Get Code Memory Size | ||||
0 | 1 | 1 | 1 | 07h | Get Data Memory Size | ||||
1 | 0 | 0 | 0 | 08h | Get Loader Version | ||||
1 | 0 | 0 | 1 | 09h | Get Utility ROM Version | ||||
1 | 0 | 1 | 0 | 0Ah | Set Word/Byte Access Mode | ||||
1 | 1 | 0 | 1 | 0Dh | Get ID Information | ||||
0 | 0 | 0 | 1 | x | x | x | x | 1 x h | Family 1—Variable-Length Load |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 10h | Load Code Variable Length |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 11h | Load Data Variable Length |
0 | 0 | 1 | 0 | x | x | x | x | 2 x h | Family 2—Variable-Length Dump |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 20h | Dump Code Variable Length |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 21h | Dump Data Variable Length |
0 | 0 | 1 | 1 | x | x | x | x | 3 x h | Family 3—Variable-Length CRC |
0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 30h | CRC Code Variable Length |
0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 31h | CRC Data Variable Length |
0 | 1 | 0 | 0 | x | x | x | x | 4 x h | Family 4—Variable-Length Verify |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 40h | Verify Code Variable Length |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 41h | Verify Data Variable Length |
0 | 1 | 0 | 1 | x | x | x | x | 5 x h | Family 5—Variable-Length Load and Verify |
0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 50h | Load/Verify Code Variable Length |
0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 51h | Load/Verify Data Variable Length |
0 | 1 | 1 | 0 | x | x | x | x | 6 x h | Family 6—Variable-Length Erase |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 60h | Erase Code Variable Length |
0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 61h | Erase Data Variable Length |
0 | 1 | 1 | 1 | x | x | x | x | 7 x h | Family 7—Reserved (for expansion) |
1 | 0 | 0 | 0 | x | x | x | x | 8 x h | Family 8—Reserved (for expansion) |
1 | 0 | 0 | 1 | x | x | x | x | 9 x h | Family 9—Fixed-Length Load |
1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 90h | Load Code Fixed Length |
1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 91h | Load Data Fixed Length |
1 | 0 | 1 | 0 | x | x | x | x | A x h | Family A —Fixed-Length Dump |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | A0h | Dump Code Fixed Length |
1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | A1h | Dump Data Fixed Length |
1 | 0 | 1 | 1 | x | x | x | x | B x h | Family B—Fixed-Length CRC |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | B0h | CRC Code Fixed Length |
1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | B1h | CRC Data Fixed Length |
1 | 1 | 0 | 0 | x | x | x | x | C x h | Family C—Fixed-Length Verify |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | C0h | Verify Code Fixed Length |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | C1h | Verify Data Fixed Length |
1 | 1 | 0 | 1 | x | x | x | x | D x h | Family D—Fixed-Length Load and Verify |
1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | D0h | Load/Verify Code Fixed Length |
1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | D1h | Load/Verify Data Fixed Length |
1 | 1 | 1 | 0 | x | x | x | x | E x h | Family E —Fixed-Length Erase |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E0h | Erase Code Fixed Length |
1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | E1h | Erase Data Fixed Length |
1 | 1 | 1 | 1 | x | x | x | x | F x h | Family F—Reserved (device specific) |
;============================================================================== ;= ;= getBanner ;= waitForPrompt ;= shiftDR ;= clock0, clock1, shift ;= ;= Executes command 0Dh to retrieve the ROM (device ID) banner and prints ;= the banner text out over the serial port. ;= ;= Inputs : None ;= Outputs : C - Set on JTAG communication error ;= Destroys : AP, APC, Acc, PSW, LC[0] ;= getBanner: call waitForPrompt jump C, getBanner_fail move Acc, #CMD_GET_ROM_BANNER call shiftDR move Acc, #00h call shiftDR getBanner_loop: move Acc, #00h call shiftDR cmp #0FFh ; The banner is ASCII, so receiving this character ; most likely indicates that the JTAG lines are ; floating high and that no device is connected jump E, getBanner_fail jump Z, getBanner_done call txChar jump getBanner_loop getBanner_done: call txNewline jump getBanner_pass getBanner_fail: move C, #1 ret getBanner_pass: move C, #0 ret
;============================================================================== ;= ;= masterErase ;= ;= Executes command 02h (Master Erase) to clear all program and data memory. ;= ;= Inputs : None ;= Outputs : C - Set on JTAG communication error ;= Destroys : Acc, PSW, LC[0], LC[1] ;= masterErase: call waitForPrompt jump C, masterErase_fail move Acc, #CMD_MASTER_ERASE call shiftDR move Acc, #00h call shiftDR move LC[1], #5000 ; Number of retries before returning an error masterErase_loop: move Acc, #CMD_NOP call shiftDR cmp #3Eh jump E, masterErase_pass move LC[0], #8000 ; Delay for about a millisecond djnz LC[0], $ djnz LC[1], masterErase_loop masterErase_pass: move C, #0 ret masterErase_fail: move C, #1 ret
org 0 ljump main org 20h main: move LCRA, #03E0h ; xxx0001111100000 ; 00 - DUTY : Static ; 0111 - FRM : Frame freq ; 1 - LCCS : HFClk / 128 ; 1 - LRIG : Ground VADJ ; 00000 - LRA : RADJ = Min move LCFG, #0F3h ; 1111xx11 ; 1111 - PCF : All segments enabled ; 1 - OPM : Normal operation ; 1 - DPE : Display enabled move LCD0, #LCD_CHAR_0 move LCD1, #LCD_CHAR_0 move LCD2, #LCD_CHAR_0 move LCD3, #LCD_CHAR_2 move LCD4, #00h sjump $然而,由于我们是从演示应用程序中装入代码字节,而不是从硬件编码的十六进制文件中装入(当采用MTK或者MAX-IDE装入代码时会有这种情况),因此,演示应用程序会根据用户输入来修改装入的应用程序。
;;;; ;;;; First load - LJUMP 0020h at start of program memory ;;;; move DP[0], #0 move @DP[0], #CMD_LOAD_CODE_VARIABLE move @++DP[0], #4 ; Length - 4 bytes move @++DP[0], #00h ; AddrL (byte address 0000h) move @++DP[0], #00h ; AddrH move @++DP[0], #000h ; 00 0B 20 0C - ljump 0020h move @++DP[0], #00Bh move @++DP[0], #020h move @++DP[0], #00Ch move @++DP[0], #000h ; Padding move @++DP[0], #000h ; Padding move @++DP[0], #55h move LC[1], DP[0] move DP[0], #0 nop call sendCommand nop jump C, main_failJTAG call getStatus jump C, main_failJTAG move Acc, A[3] ; Check that loader status is 00h (no error) jump NZ, main_failStatus以同样的方式装入其他两个存储器代码块。
;;;; ;;;; Dump program code ;;;; move DP[0], #str_dumpCodeVariable call txString move DP[0], #0 move @DP[0], #CMD_DUMP_CODE_VARIABLE move @++DP[0], #1 ; Indicates single byte length (<256 bytes) move @++DP[0], #00h ; AddrL (byte address 0000h) move @++DP[0], #00h ; AddrH move @++DP[0], #128 ; Length - 128 bytes move LC[1], #128 main_loop1: move @++DP[0], #00h djnz LC[1], main_loop1 move @++DP[0], #000h ; Padding move @++DP[0], #000h ; Padding move @++DP[0], #55h move LC[1], DP[0] move DP[0], #0 nop call sendCommand nop jump C, main_failJTAG call getStatus jump C, main_failJTAG move Acc, A[3] ; Check that loader status is 00h (no error) jump NZ, main_failStatus读取这些代码字节后,JTAG演示应用程序通过串口以十六进制格式输出这些代码字节。
;;;; ;;;; Exit loader mode and allow program code to execute ;;;; call waitForPrompt move Acc, #CMD_EXIT_LOADER call shiftDR move Acc, #00h call shiftDR move Acc, #00h call shiftDR move Acc, #00h call shiftDR
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