DshanMCU-R128s2芯片参数

描述

芯片特性

- XuanTie 64 bit RISC V C 906 CPU , up to 480 MHz
- HiFi5 Audio DSP up to 400 MHz
- Arm M33 Star MCU , up to 192 MHz

- Memories

  - 1MB SRAM

  - SiP 8 MB/16 MB Flash

  - 8 MB H S PSRAM in R128 S 1
  - 8 MB LS PSRAM & 8 MB HS PSRAM in R128 S2
  - 32 MB HS PSRAM in R128 S3
  - 2048 bit efuse

- Image and Graphics

  - Supports Graphic 2D accelerator with rotate, mixer, and 4 layers
  - Supports RGB output interface, up to 1024 x 768 @60 fps
  - Supports display engine

- Video Input

  - 8 bit parallel CSI interface
  - Supports both online and offline mode for JPEG encoder
  - Supports JPEG encoder, 1920 x 108 8

- Analog Audio Codec

  - 2 DAC channels 24 bit audio codec for R128 S1 and R128 S2
  - 1 DAC channel 24 bit for R128 S3
  - 3 ADC channels
  - Supports USB audio playback
  - Up to 119 dB SNR during DAC playback path (signal through DAC and lineout with A weighted filter)
  - Up to 98 dB SNR during ADC record path (signal through PGA and ADC with A weighted filter)

- One I2S/TDM/PCM external inte rface (I2S0

- Security Engine

  - Symmetrical algorithm: AES, DES, 3DES
  - Hash algorithm: MD5, SHA1, SHA224, SHA256, SHA384, SHA512, HMAC
  - Asymmetrical algorithm: RSA512/1024/2048bit
  - S upports TRNG

- External Peripherals

  - One USB 2.0 DRD
  - Up to 3 UART controllers (UART 0, UART1, UART2)
  - Up to 2 SPI controllers (SPI0, SPI1)
  - Up to 2 TWIs
  - One CIR RX and one CIR TX
  - Up to 8 PWM channels (PWM[ 7 0
  - Up to 7 GPADC input channels (R128 S1 & R128 S2)/8 channels (R128 S3)
  - One LEDC used to control the external intelligent control LED lamp

- Package

  - QFN80, 0.35 mm pitch, 8 mm x 8 mm body

GPIO 复用

Pin NameGPIO GroupIO TypeFunction 2Function 3Function 4Function 5Function6Function7Function8Function 14
PA0GPIOAI/OIR-RXPWM7TWI0-SCLTWI1-SCLLCD-VSYNCLCD-D2PA-EINT0
PA1/FEL0GPIOAI/OIR-TXFEM-CTRL1IR-RXTWI0-SDATWI1-SDALCD-D3PA-EINT1
PA2/FEL1GPIOAI/OSPI1-CSDMIC-DATA0JTAG-RV-TMSSDC-DATA1I2S-LRCLKJTAG-DSP-TMSLCD-D4PA-EINT2
PA3GPIOAI/OSPI1-CLKDMIC-DATA1JTAG-RV-TDISDC-DATA0I2S-BCLKJTAG-DSP-TDILCD-D5PA-EINT3
PA4GPIOAI/OSPI1-MOSIDMIC-DATA2UART0-TXSDC-CLKI2S-DINPWM1LCD-D6PA-EINT4
PA5GPIOAI/OSPI1-MISODMIC-DATA3JTAG-RV-TDOSDC-CMDI2S-DOUTJTAG-DSP-TDOLCD-D7PA-EINT5
PA6GPIOAI/OSPI1-HOLDDMIC-CLKUART0-RXSDC-DATA3I2S-MCLKLCD-CLKLCD-D14PA-EINT6
PA7GPIOAI/OSPI1-WPOWA-INJTAG-RV-TCKSDC-DATA2JTAG-DSP-TCKLCD-HSYNCLCD-D13PA-EINT7
PA8GPIOAI/OUART0-RXOWA-OUTPWM0OWA-INTWI1-SCLFEM-CTRL2LCD-D12PA-EINT8
PA9GPIOAI/OUART0-TXPWM1LEDCTWI1-SDALCD-DELCD-D15PA-EINT9
PA10GPIOAI/OUART2-RTSIR-RXPWM2TWI1-SCLLCD-D11PA-EINT10
PA11/WUPIO0GPIOAI/OUART2-CTSIR-TXPWM3TWI1-SDA32KOSCOFEM-CTRL1LCD-D10PA-EINT11
PA12/WUPIO1/ LXTAL-INGPIOAI/OUART2-TXTWI0-SCLUART2-RTSIR-RXSPI1-CS/DBI-CSXLCD-VSYNCLCD-D18PA-EINT12
PA13/WUPIO2/ LXTAL-OUTGPIOAI/OUART2-RXTWI0-SDAUART2-CTSIR-TXSPI1-CLK/DBI-SCLKLEDCLCD-D19PA-EINT13
PA14/WUPIO3GPIOAI/OPWM0SPI1-MOSIUART2-RXSIM-DATAUART1-RTSTWI1-SCLLCD-D20PA-EINT14
PA15GPIOAI/OPWM1SPI1-HOLDUART2-TXSIM-CLKUART1-CTSTWI1-SDALCD-D21PA-EINT15
PA16GPIOAI/OTWI0-SCLOWA-INTWI1-SCLUART0-TXIR-RXUART2-TXSWD-TMSPA-EINT16
PA17GPIOAI/OTWI0-SDAOWA-OUTTWI1-SDAUART0-RXIR-TXUART2-RXSWD-TCKPA-EINT17
PA18/WUPIO4GPIOAI/OI2S-MCLKIR-RXIR-TXSPI1-MOSINCSI-HSYNCLCD-VSYNCPA-EINT18
PA19/WUPIO5GPIOAI/OI2S-LRCLKUART1-RTSPWM4DMIC-DATA0SPI1-HOLDNCSI-VSYNCLCD-HSYNCPA-EINT19
PA20/WUPIO6GPIOAI/OI2S-BCLKUART1-CTSPWM5DMIC-DATA1SPI1-WPNCSI-PCLKLCD-CLKPA-EINT20
PA21/WUPIO7GPIOAI/OI2S-DINUART1-RXPWM6DMIC-DATA2SPI1-MISONCSI-MCLKLCD-DEPA-EINT21
PA22/WUPIO8GPIOAI/OI2S-DOUTUART1-TXPWM7DMIC-DATA3LEDCNCSI-D0PA-EINT22
PA23/WUPIO9GPIOAI/OI2S-MCLKDCXO-PUP-OUTSWD-SWODMIC-CLKTWI0-SCLPWM0NCSI-D1PA-EINT23
PA24GPIOAI/OSDC-DATA3SPI0-MISOPWM4UART2-RXTWI0-SDASIM-DATANCSI-D6PA-EINT24
PA25GPIOAI/OSDC-CMDSPI0-WPPWM5JTAG-M33-TDOJTAG-RV-TDOSIM-CLKNCSI-D5PA-EINT25
PA26GPIOAI/OSDC-DATA0SPI0-CLKPWM6JTAG-M33-TDIJTAG-RV-TDILEDCNCSI-D3PA-EINT26
PA27GPIOAI/OSDC-DATA1SPI0-HOLDPWM7JTAG-M33-TMSJTAG-RV-TMSSIM-DETNCSI-D2PA-EINT27
PA28GPIOAI/OSDC-DATA2SPI0-CSFEM-CTRL1JTAG-M33-TCKJTAG-RV-TCKSIM-RSTNCSI-D7PA-EINT28
PA29GPIOAI/OSDC-CLKSPI0-MOSIFEM-CTRL2UART2-TXPWM1LEDCNCSI-D4PA-EINT29

For R128-S1/S2

PB0/ADC0GPIOBI/OUART0-TXTWI1-SCLIR-RXUART2-RTSPWM2NCSI-HSYNCPB-EINT0
PB1/ADC1GPIOBI/OUART0-RXTWI1-SDAIR-TXUART2-CTSPWM3NCSI-VSYNCPB-EINT1
PB2/ADC2GPIOBI/OPWM2SPI1-MISOTWI1-SCLSIM-RSTUART1-RXUART2-RTSLCD-D23PB-EINT2
PB3/ADC3GPIOBI/OPWM3SPI1-WPTWI1-SDASIM-DETUART1-TXUART2-CTSLCD-D22PB-EINT3
PB4/ADC4GPIOBI/OPWM4LCD-DEPB-EINT4
PB14/ADC6GPIOBI/OUART1-TXNCSI-PCLKPB-EINT14
PB15/ADC7GPIOBI/OUART1-RXPWM0NCSI-MCLKPB-EINT15

For R128-S3

PB0/ADC0GPIOBI/OUART0-TXTWI1-SCLIR-RXUART2-RTSPWM2NCSI-HSYNCPB-EINT0
PB1/ADC1GPIOBI/OUART0-RXTWI1-SDAIR-TXUART2-CTSPWM3NCSI-VSYNCPB-EINT1
PB2/ADC2GPIOBI/OPWM2SPI1-MISOTWI1-SCLSIM-RSTUART1-RXUART2-RTSLCD-D23PB-EINT2
PB3/ADC3GPIOBI/OPWM3SPI1-WPTWI1-SDASIM-DETUART1-TXUART2-CTSLCD-D22PB-EINT3
PB4/ADC4GPIOBI/OUART1-RTSSDC-CLKSPI0-CSPWM4LCD-DEPB-EINT4
PB5/ADC5GPIOBI/OUART1-CTSSDC-DATA1SPI0-MOSIPWM5PB-EINT5
PB6GPIOBI/OUART1-TXSDC-DATA0SPI0-CLKPWM6PB-EINT6
PB7GPIOBI/OUART1-RXSDC-DATA3SPI0-HOLDPWM7PB-EINT7
PB14/ADC6GPIOBI/OUART1-TXSDC-DATA2SPI0-WPNCSI-PCLKPB-EINT14
PB15/ADC7GPIOBI/OUART1-RXSDC-CMDSPI0-MISOPWM0NCSI-MCLKPB-EINT15

信号描述

Signal NameDescriptionType
HS-PSRAM PHY IO
VDD12-PSMPower Supply of PSRAMP
RF0
ANT0Antenna of RF0A
HXTAL-INDigital Compensated Crystal Oscillator InputAI
HXTAL-OUTDigital Compensated Crystal Oscillator OutputAO
VCC33-RFPA0Power Supply of RF0 InputP
VCC18-TX0Power Supply of RF0 InputP
VCC18-ANA0Power Supply of RF0 Analog/RF InputP
Note: HXTAL is the system clock of the whole chip, which includes the clocks required by the RF module and other modules.
RF1
ANT1Antenna of RF1A
VCC33-RFPA1Power Supply of RF1 InputP
VDD18-TX1Power Supply of RF1 InputP
VCC18-ANA1Power Supply of RF1 Analog/RF InputP
PMU
VIN-VBATVBAT System Power InputP
VDD-RTCRTC PowerP
VDD-AONVDD-AON Power Supply of AON DomainP
VDD-DSPVDD-DSP Power Supply of DSPP
LXPower Supply of DCDC OutputP
EXT-LDO33VDD-3V3 Power Output of 3.3VP
VDD-SENSEPower Supply of Internal LDO InputP
VDD-SYSPower Supply for SystemP
RESET
CHIP-PWDSystem Power on ResetI
RSTNSystem ResetI
USB
VC33-USBPower Supply of USBP
USB-DMUSB Data Signal DMA I/O
USB-DPUSB Data Signal DPA I/O
Audio Codec
MBIASMaster Analog Microphone Bias Voltage OutputAO
MICIN1PMicrophone Positive Input 1AI
MICIN1NMicrophone Negative Input 1AI
MICIN2PMicrophone Positive Input 2AI
MICIN2NMicrophone Negative Input 2AI
MICIN3PMicrophone Positive Input 3AI
MICIN3NMicrophone Negative Input 3AI
VRA1Reference VoltageAO
VRA2Reference VoltageAO
AGNDAnalog GroundG
AVCCPower Supply for Analog PartP
LOUTRNStereo Lineout Output Right Negative ChannelAO
LOUTRPStereo Lineout Output Right Positive ChannelAO
LOUTLPStereo Lineout Output Left Positive ChannelAO
LOUTLNStereo Lineout Output Left Negative ChannelAO
Power
VCC-IO1Power Supply of IO1 DomainP
VCC-IO2Power Supply of IO2 DomainP
CIR Receiver
IR-RXConsumer Infrared ReceiverI/O
CIR Transmitter
IR-TXConsumer Infrared TransmitterI/O
SPI
SPI0-CSSPI0 Chip Select Signal, Low ActiveI/O
SPI0-CLKSPI0 Clock SignalI/O
SPI0-MOSISPI0 Master Data Out, Slave Data InI/O
SPI0-MISOSPI0 Master Data In, Slave Data OutI/O
SPI0-WPSPI0 Write Protect, Low ActiveI/O
SPI0-HOLDSPI0 Hold SignalI/O
SPI1-CSSPI1 Chip Select Signal, Low Active/Chip Select Signal, Low ActiveI/O
SPI1-CLKSPI1 Clock Signal/Serial Clock SignalI/O
SPI1-MOSISPI1 Master Data Out, Slave Data In/Data Output SignalI/O
SPI1-MISOSPI1 Master Data In, Slave Data Out/Data Input Signal/Tearing Effect Input/DCX pin is the select output signal of data and commandI/O
SPI1-HOLDSPI1 Hold Signal/ DCX pin is the select output signal of data and command/When DBI operates in dual data lane format, the RGB666 format 2 can use WRX to transfer dataI/O
SPI1-WPSPI1 Write Protect, Low Active/ Tearing Effect InputI/O
UART
UART0-RXUART0 Data ReceiveI/O
UART0-TXUART0 Data TransmitI/O
UART1-RTSUART1 Data Request to SendI/O
UART1-CTSUART1 Data Clear to SendI/O
UART1-RXUART1 Data ReceiveI/O
UART1-TXUART1 Data TransmitI/O
UART2-RTSUART2 Data Request to SendI/O
UART2-CTSUART2 Data Clear to SendI/O
UART2-RXUART2 Data ReceiveI/O
UART2-TXUART2 Data TransmitI/O
PWM
PWM[7:0]Pulse Width Modulation Output Channel0I/O
TWI
TWI0-SCLTWI0 Serial CLOCK SignalI/O
TWI0-SDATWI0 Serial Data SignalI/O
TWI1-SCLTWI1 Serial CLOCK SignalI/O
TWI1-SDATWI1 Serial Data SignalI/O
I2S
I2S-LRCLKI2S sample rate clockI/O
I2S-BCLKI2S Bit Rate ClockI/O
I2S-DINI2S Serial Data InputI/O
I2S-DOUTI2S Serial Data InputI/O
I2S-MCLKI2S Master ClockI/O
SDIO
SDC-CMDSDIO Command SignalI/O
SDC-DATA[3:0]SDIO data SignalI/O
SDC-CLKSDIO clock SignalI/O
DMIC
DMIC-DATA[3:0]Digital MIC Data input signalI/O
DMIC-CLKDigital Microphone Clock OutputI/O
OWA
OWA-INOne Wire Audio InputI/O
OWA-OUTOne Wire Audio OutputI/O
JTAG
JTAG-RV-TMSRISC-V JTAG TMS signalI/O
JTAG-DSP-TMSDSP JTAG TMS signalI/O
JTAG-RV-TDIRISC-V JTAG TDI signalI/O
JTAG-DSP-TDIDSP JTAG TDI signalI/O
JTAG-RV-TDORISC-V JTAG TDO signalI/O
JTAG-DSP-TDODSP JTAG TDO signalI/O
JTAG-RV-TCKRISC-V JTAG TCK signalI/O
JTAG-DSP-TCKDSP JTAG TDO signalI/O
JTAG-M-TDOARM M33 JTAG TDO signalI/O
JTAG-M-TDIARM M33 JTAG TDI signalI/O
JTAG-M-TMSARM M33 JTAG TMS signalI/O
JTAG-M-TCKARM M33 JTAG TCK signalI/O
SWD
SWD-SWOSerial Wire Debug data signalI/O
SWD-TMSSerial Wire Debug TMS signalI/O
SWD-TCKSerial Wire Debug clock signalI/O
System
FEM-CTRL1Front End Module Control, TX-ENI/O
FEM-CTRL2Front End Module Control, RX-ENI/O
SIM-DATASmart Card data signalI/O
SIM-CLKSmart Card clock signalI/O
SIM-DETSmart Card detect signalI/O
SIM-RSTSmart Card reset signalI/O
DCXO
DCXO-PUP-OUTPower Control of External DCDCI/O
LEDC
LEDCIntelligent control LED signal outputI/O
CLOCK
32KOSCO32.768K clock fanoutI/O
LCD
LCD-VSYNCLCD Vertical SyncI/O
LCD-D[7:2]LCD Data OutputI/O
LCD-D[15:10]LCD Data OutputI/O
LCD-D[23:18]LCD Data OutputI/O
LCD-CLKLCD CLOCKI/O
LCD-HSYNCLCD Horizontal SyncI/O
LCD-DELCD Data Output EnableI/O
NCSI
NCSI-HSYNCDVP-CSI Horizontal Sync signalI/O
NCSI-VSYNCDVP-CSI Vertical Sync signalI/O
NCSI-PCLKDVP-CSI pixel clock signalI/O
NCSI-MCLKDVP-CSI master clock signalI/O
NCSI-D[7:0]DVP-CSI data signal[7:0]I/O
Interrupt
PA_EINT[29:0]GPIO A InterruptI/O
PB_EINT[4:0]GPIO B InterruptI/O
PB_EINT[15:14]GPIO B InterruptI/O

R128-S1/R128-S2 与 R128-S3 的引脚区别

Ball NumberR128-S1/R128-S2 PinR128-S3 Pin
19RSTNVIN-VBAT
20VIN-VBATLX
21LXVDD-SENSE
22VDD-SENSEVCC33-USB
23VCC33-USBUSB-DM
24USB-DMUSB-DP
25USB-DPVDD-SYS
26VDD-SYSVDD12-PSM
27VDD12-PSMPA16
28PA16PA17
29PA17PA15
30PA15PA27
31PA27PA26
32PA26PA29
33PA29PA25
34PA25PA24
35PA24PA28
36PA28PB7
39PB14/ADC6PB6
40PB15/ADC7PB5/ADC5
41PB1/ADC1PB14/ADC6
42PB0/ADC0PB15/ADC7
43PB4/ADC4PB0/ADC0
44VDD-SYSPB1/ADC1
45VCC-IO1PB4/ADC4
46MBIASVDD-SYS
47MICIN1PVCC-IO1
48MICIN1NMBIAS
49MICIN2PMICIN1P
50MICIN2NMICIN1N
51MICIN3PMICIN2P
52MICIN3NMICIN2N
53VRA1MICIN3P
54VRA2MICIN3N
55AGNDVRA1
56AVCCVRA2
57LOUTLNAGND
58LOUTLPAVCC
59LOUTRPLOUTLN
60LOUTRNLOUTLP
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