xapp333代码

xapp333代码

THIS DESIGN IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS,
EXPRESS, IMPLIED,  STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES
OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. This design has not been
verified on hardware (as opposed to simulations), and it should be used only as an example design,
not as a fully functional core. XILINX does not warrant the performance, functionality, or operation
of this Design will meet your requirements, or that the operation of the Design will be uninterrupted
or error free, or that defects in the Design will be corrected. Furthermore, XILINX does not warrant
or make any representations regarding use or the results of the use of the Design in terms of
correctness, accuracy, reliability or otherwise.

THIRD PARTIES INCLUDING PHILIPS MAY HAVE PATENTS ON THE INTER-INTEGRATED CIRCUIT ("I2C") BUS.  BY
PROVIDING THIS HDL CODE AS ONE POSSIBLE IMPLEMENTATION OF THIS STANDARD, XILINX IS MAKING NO
REPRESENTATION THAT THE PROVIDED IMPLEMENTATION OF THE I2C BUS IS FREE FROM ANY CLAIMS OF INFRINGEMENT
BY ANY THIRD PARTY.  XILINX EXPRESSLY DISCLAIMS ANY WARRANTY OR CONDITIONS, EXPRESS, IMPLIED,
STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY,
NON-INFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE,  THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING
BUT NOT LIMITED TO ANY  WARRANTY OR REPRESENTATION THAT THE IMPLEMENTATION IS FREE FROM CLAIMS OF ANY
THIRD PARTY.  FURTHERMORE, XILINX IS PROVIDING THIS REFERENCE DESIGNS "AS IS" AS A COURTESY TO YOU.
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File Contents
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This zip file contains the following folders:

 \work    -- XST and ModelSim compiled VHDL files

 -- VHDL Source Files:
  i2c.vhd   -- top level file
  i2c_control.vhd  -- control function for the I2C master/slave
  shift.vhd  -- shift register
  uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC
  upcnt4.vhd  -- 4-bit up counter
  i2c_timesim.vhd  -- post-route I2C simulation netlist
     
 --VHDL Testbench Files: 
  micro_test.vhd  -- top-level VHDL testbench for functional simulation that
        instantiates micro_tb.vhd, pullup.vhd, and i2c.vhd. 
 
  micro_tb.vhd  -- VHDL functional simulation testbench that tests two
        instantiations of the I2C design. It configures
        one as a master and one as a slave and then
        the two I2C designs transfer data over I2C.

  micro_test_post.vhd -- top-level VHDL testbench for post-route simulation that
        instantiates micro_master_tb.vhd, micro_slave_tb.vhd,
        pullup.vhd and the post-route VHDL model time_sim.vho
  micro_master_tb.vhd 
  micro_slave_tb.vhd -- These two files test the post-fit VHDL files output from
        Project Navigator. Since in the post-fit VHDL the uC
        address is hard-coded,  both instantiations of the I2C
        design have the same uC address. Therefore separate
        testbenches are needed to talk to the two instantiations
        of the I2C design; one that configures one of the I2C
        designs as a Master, one that configures the other I2C
        design as a Slave.
  pullup.vhd  -- models a pull-up resistor
  upcnt4_tb.vhd  -- functional testbench for upcnt4
  upcnt4_tb_post.vhd -- post-route testbench for upcnt4

 -- ModelSim DO files: 
  micro_test.do  -- functional simulation script file that calls wave.do
  wave.do   -- configures wave window for functional simulation
  micro_test_post.do -- post-route simulation script file that calls wave_post.do
  wave_post.do  -- configures wave window for post-route simulation

 -- Report Files
  i2c.rpt   -- Project Navigator fitter report file
  i2c.cxt   -- XPower input data file
 
 -- XST Files
  i2c.npl   -- Project Navigator project file
  i2c.jed   -- JEDEC programming file with I2C fit to a XCR3256XL-7-TQ144
        device