Xilinx CORE生成器IP列表名称及说明详解

本页包含通过LabVIEW FPGA模块可用的Xilinx CORE生成器IP的列表。LabVIEW通过Xilinx IP节点实现该IP。

下列IP名称和说明来自于Xilinx数据表。LabVIEW仅支持FPGA设备支持的IP。并非全部FPGA设备系列均支持所有IP。关于FPGA设备支持的详细信息，见IP数据表。单击Xilinx内核生成器配置对话框的数据表按钮，了解IP内核的详细信息。

注： Xilinx提供并维护Xilinx内核生成器IP。由于Xilinx可能不再支持或更新早期版本的IP内核。NI仅能确保支持通过FPGA终端的Xilinx工具的当前版本创建的.xco文件的IP集成节点。Xilinx网站 上提供了已废弃的IP内核的列表。

Xilinx为Xilinx内核生成器IP提供许可证。在特定Xilinx内核生成器IP的即时帮助窗口，可查看许可证信息。将.lic文件放置在C:\NIFPGA\programs\XilinxY_Z\ISE\coregen\core_licenses目录下可导入许可证。其中XilinxY_Z是用于FPGA终端的Xilinx工具的当前版本。

“Xilinx内核生成器IP”函数选板可能包含需要额外获取Xilinx许可证的IP内核。添加上述IP内核至程序框图时，LabVIEW显示包含Xilinx许可证资源信息的错误消息。如用户已获取Xilinx许可证，必须在带有许可证的计算机上编译包含许可IP的VI。

.3GPP Downlink Chip Rate—The 3GPP Downlink Chip Rate core provides a Release 6 Compliant, Xilinx FPGA optimized solution for Femto-cell, Pico-cell and Macro-cell solutions. The Xilinx Downlink Chip Rate LogiCORE is fully synchronous, using a single clock. The Downlink Chip Rate Core incorporates Xilinx Smart-IP technology for maximum performance. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Telecommunications, Wireless)

.3GPP LTE Channel Estimator—The 3GPP LTE Channel Estimator v1.0 core implements channel estimation functionality for uplink LTE eNodeB applications based on the 3GPP TS 36.211 specification.(Communication & Networking, Wireless)

.3GPP LTE MIMO Encoder—The LTE 3GPP MIMO Encoder v2.0 core implements multiple-input, multiple-output (MIMO) encoding for LTE eNodeB applications as defined in the 3GPP TS 36.211 specification.(Communication & Networking, Wireless)

.3GPP RACH Preamble Detector—The 3GPP RACH Preamble Detector core provides an optimal solution for implementing RACH detection in a 3GPP uplink. The core includes all of the logic required for scramble-code generation, correlation and preamble detection. The RACH Preamble Detector combines an optimal core and a flexible wrapper design. (Communication & Networking, Telecommunications, Wireless)

.3GPP Searcher—The 3GPP Searcher core is a highly integrated solution for identifying the multiple transmission paths of users in a 3GPP uplink. The core includes all the logic required for scramble code generation, correlation, accumulation and filtering in a single co-processor, easily integrated with a DSP or microprocessor. (Communication & Networking, Telecommunications, Wireless)

.3GPP Turbo Decoder—The Turbo Decoder LogiCORE from Xilinx is a high-performance, compact Turbo Decoder which meets the 3GPP specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.3GPP Turbo Encoder—The Turbo encoder LogiCORE from Xilinx is a high-speed, compact Turbo Encoder which meets the 3GPP specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.3GPP2 Turbo Decoder—Rev 1. The 3GPP2 Turbo Decoder from Xilinx is a high-speed, compact core which offers support for specifications, '3GPP2 C.S0024-A V2.0' and '3GPP2 C.S0024-B V1.0'. The Turbo Decoder core is parameterizable allowing the designer to trade-off Bit Error Rate (BER) against core complexity and performance. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications )

.3GPP2 Turbo Encoder—Rev 1. The Turbo encoder LogiCORE from Xilinx is a high-speed, compact Turbo Convolutional Encoder which meets the 3GPP2 C.S0024-B specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.3GPPLTE Turbo Decoder—The Turbo Decoder LogiCORE from Xilinx is a high-performance, compact Turbo Decoder which meets the 3GPP LTE specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.3GPPLTE Turbo Encoder—The Turbo encoder LogiCORE from Xilinx is a high-speed, compact Turbo Encoder which meets the 3GPP LTE specification. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.802.16e CTC Decoder—The 802.16e CTC Decoder LogiCORE is a drop-in module for Virtex-4(TM), Virtex-5(TM), Virtex-6(TM), Spartan-3(TM), Spartan-3E(TM), Spartan-3A DSP(TM) and Spartan-6(TM) families of FPGA. It performs iterative soft decoding of channel data that has been encoded as described in Section 8.4.9.2.3 of the IEEE Std 802.16e-2005 specification and the corrigendum IEEE P802.16Rev2/D0b (June 2007). The core is fully synchronous, using a single clock, and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.802.16e CTC Encoder—The Xilinx 802.16e Convolutional Turbo Coder LogiCORE is a drop-in module for Virtex-4(TM), Virtex-5(TM), Virtex-6(TM), Spartan-3(TM) and Spartan-6(TM) families of FPGA. It is a high-speed, compact module for generating coded data streams according to the IEEE Std 802.16e-2005 and IEEE Std 802.16-2004/Cor1-2005 standard, OFDMA PHY layer. (Section 8.4.9.2.3) The core is fully synchronous, using a single clock, and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.Accumulator—The Xilinx LogiCORE Accumulator can generate adder- subtractor- and adder/subtractor-based accumulators operating on signed or unsigned input. Inputs range from 1 to 256 bits wide, and outputs, from 1 to 258 bits. (Basic Elements, Accumulators)

.Adder Subtracter—The Xilinx LogiCORE Adder Subtracter can create adders, subtracters, and adders/subtracters that operate on signed or unsigned data. In fabric, the module supports inputs ranging from 1 to 256 bits wide, and outputs ranging from 1 to 258 bits wide. I/O widths are family dependent for dsp48 implementations. (Math Functions, Adders & Subtractors)

.Binary Counter—The Xilinx LogiCORE Binary Counter creates up counters, down counters, and up/down counters with output widths ranging up to 256 bits. The upper count limit is user programmable, and the counter's increment value can either be user-defined, or specified via an external input port. (Basic Elements, Counters)

.Block Memory Generator—The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCORES, please consult the data sheet. (Basic Elements, Memory Elements, Memories & Storage Elements, RAMs & ROMs)

.CIC Compiler—The Xilinx CIC Compiler LogiCORE is a module for design and implementation of Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices. (Digital Signal Processing, Filters)

.Color Correction Matrix—The Xilinx Color Correction Matrix LogiCORE can be used for color correction operations such as adjusting white balance, color cast, brightness, or contrast in an RGB image. The implementation is a 3x3 programmable coefficient matrix multiplier with offset compensation. (Video & Image Processing)

.Color Filter Array Interpolation—The Xilinx LogiCORE Color Filter Array Interpolation Core reconstructs RGB data from color image sensors equipped with a Bayer Color Filter Array. (Video & Image Processing)

.Complex Multiplier—Complex multiplication is a basic DSP operation. All operands, as well as the results, are represented as signed two's-complement data. Operand widths and result widths are parameterizable. Operand widths up to 63 bits are supported.

.Convolutional Encoder—The Convolutional Encoder LogiCORE from Xilinx is a high-speed, compact convolutional encoder with a puncturing option. The Convolutional Encoder core is parameterizable, allowing the designer to control the constraint length and the type of convolutional and puncture code. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.CORDIC—The Xilinx CORDIC LogiCORE is a module for generation of the generalized coordinate rotational digital computer (CORDIC) algorithm which iteratively solves trigonometric, hyperbolic and square root equations. The core is fully synchronous using a single clock. Options include parameterizable data width and control signals. The core supports either serial architecture for minimal area implementations, or parallel architecture for speed optimization. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Math Functions, Conversions, CORDIC, Square Root, Trig Functions, Digital Signal Processing, Building Blocks)

.DDS Compiler—The Xilinx DDS Compiler LogiCORE provides Direct Digital Synthesizers (DDS) and optionally either Phase Generator or Sine/Cosine Lookup Table constituent parts as independent cores. The core features sine, cosine or quadrature outputs with 3 to 26-bit output sample precision. The core supports up to 16 channels by time-sharing the sine/cosine table, which dramatically reduces the area requirement when multiple channels are needed. Phase Dithering and Taylor Series Correction options provide high dynamic range signals using minimal FPGA resources. In addition, the core has an optional phase offset capability, providing support for multiple synthesizers with precisely controlled phase differences.

.Digital Pre-distortion—Digital Pre-distortion (DPD) is an important component in the signal processing chains of many wireless communications systems. The Xilinx DPD LogiCORE provides users an off-the-shelf means to integrate this functionality in their Digital radio Front End (DFE) design for a range of wireless interface standards based on system-level parameters. The core also offers an unique option to customize the solution to allow users to add their proprietary Pre-distortion algorithm implementation for the given hardware features. The core implementation is delivered through the Xilinx CORE Generator system, and is designed to take advantage of the advanced features of Xilinx FPGA devices. (Communication & Networking, Wireless)

.Discrete Fourier Transform—The Discrete Fourier Transform (DFT) core has been specifically designed to meet the needs of the LTE standard, in terms of point sizes, low latency and resource requirements. (Digital Signal Processing, Transforms, DFTs)

.Distributed Memory Generator—The LogiCORE Xilinx Distributed Memory Generator creates area and performance optimized ROM blocks, single and dual port distributed memories, and SRL16-based memories for Xilinx FPGAs. The core supersedes the previously released LogiCORE Distributed Memory core. Use this core in all new designs for supported families wherever a distributed memory is required. (Basic Elements, Memory Elements, Memories & Storage Elements, RAMs & ROMs)

.Divider Generator—This core provides division using one of two algorithms. The Radix-2 algorithm provides a fabric solution suitable for smaller operand division, and High Radix algorithm provides a solution based upon XtremeDSP slices and so is well suited to larger operands (that is above about 16 bits wide). (Math Functions, Dividers)

.DSP48 Macro—The Xilinx LogiCORE DSP48 Macro provides an easy to use interface which abstracts the XtremeDSP Slice configuration and simplifies its dynamic operation by enabling the specification of multiple operations via a set of user defined arithmetic expressions. The operations are enumerated and can be selected by the user via single port on the generated IP. (Basic Elements)

.DUC/DDC Compiler—Digital Up/Down Converters (DUC/DDC) are important components in the signal processing chains of many digital communications systems. The Xilinx DUC/DDC Compiler LogiCORE provides users with means to rapidly implement these functions for a range of wireless interface standards based on system-level parameters. The core implementation is delivered through the Xilinx CORE Generator system, and is designed to take advantage of the advanced features of Xilinx FPGA devices. (Communication & Networking, Wireless, Digital Signal Processing, Filters)

.DVB S2 FEC Encoder—The DVB-S2 FEC Encoder LogiCORE is a high speed FEC encoder for the DVB-S2 standard, ETSI EN 302 307 V1.1.2. The core is fully synchronous, using a single clock. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.Fast Fourier Transform—The Fast Fourier Transform (FFT) is a computationally efficient algorithm for computing the Discrete Fourier Transform (DFT). The FFT Core can compute 8 to 65536-point forward or inverse complex transforms on up to 12 parallel channels. The input data is a vector of complex values represented as two's-complement numbers 8 to 34 bits wide or single precision floating point numbers 32 bits wide. The phase factors can be 8 to 34 bits wide. All memory is on-chip using either Block RAM or Distributed RAM. Three arithmetic types are available: full-precision unscaled, scaled fixed-point, and block-floating point. Several parameters are run-time configurable: the point size, the choice of forward or inverse transform, and the scaling schedule. Four architectures are available to provide a tradeoff between size and transform time.

.FIFO Generator—The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains as well as optional fixed or programmable full and empty flags and handshaking signals. Select from multiple memory resource types for implementation. The FIFO Generator includes optional Hamming code-based error detection and correction as well as error injection capability for system test help to ensure data integrity. The FIFO Generator also supports parameterizable width and depth. For native interface FIFOs, the FIFO Generator supports asymmetric read and write port widths. (Memories & Storage Elements, FIFOs)

.FIR Compiler—The Xilinx FIR Compiler LogiCORE is a module for generation of high speed, compact filter implementations that can be configured to implement many different filtering functions. The core is fully synchronous, using a single clock, and is highly parameterizable, allowing designers to control the filter type, data and coefficient widths, the number of filter taps, the number of channels, etc. Multi-rate operation is supported. The user can specify the implementation method, with a choice of Multiply-Accumulate or Distributed Arithmetic architectures. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow.(Memories & Storage Elements, FIFOs)

.Floating-Point—The Xilinx Floating-Point Operator is capable of being configured to provide a range of floating-point operations. The core offers addition, subtraction, multiplication, division, square-root, compare and conversion operations. High-speed, with single-cycle throughput is provided at a wide range of word lengths that includes both single and double precision. Embedded multipliers or XtremeDSP slices can be used with certain operations. (Math Functions, Floating Point)
Gamma Correction—The Xilinx Gamma Correction LogiCORE provides customers with a fully tested and optimized hardware block for manipulating the values of a pixel. The input video data to be adjusted for specific output display devices by applying gamma curves to be applied to each color channel independently or as a single curve to all channels. This core supports a LUT table structure, or an interpolated LUT table structure that is programmed to transform the image data for the best image quality on the display. (Video & Image Processing)

.Image Edge Enhancement—The Xilinx Edge Enhancement LogiCORE provides edge enhancement of each frame of video data being processed. The core provides a set of standard Sobel and Laplacian filters with programmable, edge adaptive gain settings to adjust the strength of the edge enhancement effect. (Video & Image Processing)

.Image Noise Reduction—The Xilinx Noise Reduction LogiCORE provides developers with an easy to use IP block for reducing noise within each frame of video. The core has a programmable, edge adaptive smoothing function to change the characteristics of the filtering in real-time. (Video & Image Processing)

.Interleaver/De-interleaver—The Xilinx Interleaver/De-interleaver LogiCORE module is a high speed, compact design and implements either the Forney Convolutional or Rectangular Block type architecture. For the Convolutional type, the number of branches and branch lengths are parameterizable. For the Rectangular Block type the number of rows and columns is parameterizable or run-time variable. Row and column permutations are also supported. The core supports a symbol size ranging from 1 to 256 bits. The core incorporates Xilinx Smart-IP technology for maximum performance. It is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.LDPC 802 16 Encoder—The Xilinx 802.16e Low Density Parity Check code Encoder LogiCORE is a drop in module for Virtex-II(TM), Virtex-4(TM) and Spartan-3(TM) families of FPGA. It is a high-speed, compact module for generating data streams according to the IEEE 802.16e-2005 (draft 6) standard, OFDMA PHY layer. (Section 8.4.9.2.5) The core is fully synchronous, using a single clock, and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.LTE DL Channel Encoder—The LTE DL Channel Encoder core provides designers with an LTE Downlink Channel Encoding block for the 3GPP TS 36.212 v8.5.0 Multiplexing and channel coding specification. (Communication & Networking, Telecommunications, Wireless)

.LTE Fast Fourier Transform—The LTE Fast Fourier Transform LogiCORE(TM) implements all transform lengths required by the 3GPP LTE specification, including the 1536-point transform for 15 MHz bandwidths. The transform length, transform direction, cyclic prefix length and scaling schedule may be configured on a per-frame basis. (Communication & Networking, Telecommunications, Wireless, Digital Signal Processing, Transforms, FFTs)

.LTE RACH Detector—LTE RACH decoder. (Communication & Networking, Telecommunications)

.LTE UL Channel Decoder—The LTE UL Channel Decoder core provides designers with an LTE Uplink Channel Decoder block for the 3GPP TS 36.212 v8.5.0 Multiplexing and channel coding specification. (Communication & Networking, Telecommunications, Wireless)

.Motion Adaptive Noise Reduction—The Xilinx Motion Adaptive Noise Reduction LogiCORE is an effective module for both motion detection and motion adaptive noise reduction in video streams. The core allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed. The noise reduction algorithm is implemented as a recursive temporal filter with a user programmable transfer function allowing the user to control both the shape of the motion transfer and the strength of the noise reduction applied. The motion transfer function is initialized according to the settings in the Coregen GUI, but is also programmable at runtime via the register interface. The LogiCORE is provided with two different interfaces: General purpose processor and EDK Pcore (including device driver). (Video & Image Processing)

.Multiplier—Multiplication is a fundamental DSP operation. This core allows parallel and constant-coefficient multipliers to be generated. The user can specify if dedicated hardware multipliers, slice logic or a combination of resources should be utilized. (Math Functions, Multipliers)

.Multiply Accumulator—The Xilinx LogiCORE Multiply Accumulator generates a multiply accumulate function implemented in Xtreme DSP(TM) slices. User options allow you to specify the word lengths of the inputs and the accumulation width. (BaseIP)

.Multiply Adder—The Xilinx LogiCORE Multiply Adder generates a multiply-add function implemented in Xtreme DSP(TM) slices. User options allow you to specify the word lengths of the inputs and output. Optimal pipelining for maximum speed and no pipelining are available. (BaseIP)

.Peak Cancellation Crest Factor Reduction—The Peak Cancellation Crest Factor Reduction LogiCORE(TM) provides a flexible and highly efficient solution to reduce the peak to average power ratio (PAR) of complex multi-carrier waveforms. (Communication & Networking, Wireless)

.RAM-based Shift Register—The Xilinx LogiCORE RAM-based Shift Register generates fast, compact FIFO-style registers, delay lines or time-skew buffers up to 256 bits wide and up to 1024 words deep using Select RAM in SRL16 or SRLC32 mode. User options allow you to create either fixed-length or variable-length shift registers, as well as to specify output register capability with clock enable and synchronous controls. (Basic Elements; Registers, Shifters, & Pipelining)

.Reed-Solomon Decoder—The Xilinx Reed-Solomon Decoder LogiCORE is a high speed, compact module that can be configured to implement many different Reed-Solomon coding standards. The core is fully synchronous, using a single clock, and supports continuous input data with no gap between code blocks. The core is parameterizable, allowing designers to control the symbol size, the code block length, the number of errors corrected, and the control signal behavior. The Decoder supports both error and erasure decoding. It is delivered through the Xilinx CORE Generator system and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.Reed-Solomon Encoder—The Xilinx Reed-Solomon Encoder LogiCORE is a high speed, compact module that can be configured to implement many different Reed-Solomon coding standards. The core is fully synchronous, using a single clock, and supports continuous input data with no gap between code blocks. The core is parameterizable, allowing designers to control the symbol width and the code block length. The module supports shortened codes and any primitive field polynomial for a given symbol width. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.RGB to YCrCb Color-Space Converter—The Xilinx RGB to YCrCb Color Space Converter LogiCORE with built-in support for 5 formats and 3 range standards. The implementation is a simplified 3x3 constant coefficient matrix multiplier, which uses only 4 multipliers exploiting the inter-relations of RGB to YCrCb coefficients. The module is optimized to take advantage of multiply-add capabilities of DSP slices. (Video & Image Processing)

.Video On Screen Display—The Xilinx On-Screen Display LogiCORE provides a flexible video processing block for alpha blending and compositing as well as simple text and graphics generation. Support for up to eight layers using a combination of external video inputs (from frame buffer) and internal graphics controllers (including text generators) is provided. Supported image sizes up to 4kx4k with YUVa 4:4:4 or 4:2:2 and RGBa image formats up to 1080p 30fps. The core is programmable through a comprehensive register interface for setting and controlling screen size, background color, layer position, and more using logic or a microprocessor. A comprehensive set of interrupt status bits is provided for processor monitoring. The LogiCORE is provided with two different interfaces: General Purpose Processor and EDK Pcore (including device driver). (Video & Image Processing)

.Video Timing Controller—The Xilinx Video Timing Controller LogiCORE(TM) is a general purpose video timing generator and detector. Automatic detection of horizontal and vertical front and back porches, sync pulses and active video pixels is provided along with sync and blank pulse polarity detection. Horizontal and vertical blanking and sync pulses are generated including support for programmable pulse polarity. The core is programmable through a comprehensive register set allowing control of various timing generation parameters including horizontal and vertical front and back porch start, active video start, sync start and more. A comprehensive set of interrupt status bits is provided for processor monitoring. (Video & Image Processing)

.Viterbi Decoder—The Xilinx Viterbi Decoder LogiCORE is fully synchronous, using a single clock. Options include parameterizable constraint length, convolutional codes and traceback length. Various architectures are available including parallel, serial, multi-channel and dual decoding. The core is delivered through the Xilinx CORE Generator System and integrates seamlessly with the Xilinx design flow. (Communication & Networking, Error Correction, Telecommunications)

.YCrCb to RGB Color-Space Converter—The Xilinx YCrCb to RGB Color Space Converter LogiCORE with built-in support for 4 video standards and 3 input ranges. The implementation is a simplified 3x3 constant coefficient matrix multiplier, which uses only 4 multipliers exploiting the inter-relations of color-space conversion coefficients. The module is optimized to take advantage of multiply-add capabilities of DSP slices. (Video & Image Processing)