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74HC259 pdf datasheet
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2008-08-06
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MM54HC259/MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
This device utilizes advanced silicon-gate CMOS technology
to implement an 8-bit addressable latch, designed for
general purpose storage applications in digital systems.
The MM54HC259/MM74HC259 has a single data input (D),
8 latch outputs (Q1±Q8), 3 address inputs (A, B, and C), a
common enable input (G), and a common CLEAR input. To
operate this device as an addressable latch, data is held on
the D input, and the address of the latch into which the data
is to be entered is held on the A, B, and C inputs. When
ENABLE is taken low the data flows through to the addressed
output. The data is stored when ENABLE transitions
from low to high. All unaddressed latches will remain
unaffected. With enable in the high state the device is deselected,
and all latches remain in their previous state, unaffected
by changes on the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches,
the enable should be held high (inactive) while the address
lines are changing.
If enable is held high and CLEAR is taken low all eight latches
are cleared to a low state. If enable is low all latches
except the addressed latch will be cleared. The addressed
latch will instead follow the D input, effectively implementing
a 3-to-8 line decoder.
All inputs are protected from damage due to static discharge
by diodes to VCC and ground.
Features
Y Typical propagation delay: 18 ns
Y Wide supply range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA maximum (74HC Series)
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
This device utilizes advanced silicon-gate CMOS technology
to implement an 8-bit addressable latch, designed for
general purpose storage applications in digital systems.
The MM54HC259/MM74HC259 has a single data input (D),
8 latch outputs (Q1±Q8), 3 address inputs (A, B, and C), a
common enable input (G), and a common CLEAR input. To
operate this device as an addressable latch, data is held on
the D input, and the address of the latch into which the data
is to be entered is held on the A, B, and C inputs. When
ENABLE is taken low the data flows through to the addressed
output. The data is stored when ENABLE transitions
from low to high. All unaddressed latches will remain
unaffected. With enable in the high state the device is deselected,
and all latches remain in their previous state, unaffected
by changes on the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches,
the enable should be held high (inactive) while the address
lines are changing.
If enable is held high and CLEAR is taken low all eight latches
are cleared to a low state. If enable is low all latches
except the addressed latch will be cleared. The addressed
latch will instead follow the D input, effectively implementing
a 3-to-8 line decoder.
All inputs are protected from damage due to static discharge
by diodes to VCC and ground.
Features
Y Typical propagation delay: 18 ns
Y Wide supply range: 2±6V
Y Low input current: 1 mA maximum
Y Low quiescent current: 80 mA maximum (74HC Series)
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2011-10-13
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