EAI3576-Core-T（RK3576 核心板）产品数据全解
描述
典型应用
1.功能简介
1.1产品简介
EAI3576-Core-T是灵眸科技研发的一款应用于AIoT领域的核心板。核心板基于瑞芯微的RK3576处理器设计，集成了4个Cortex-A72和4个Cortex-A53及独立的NEON协处理器，支持4K@120fps的H.265，VP9AVS2 和 AV1解码器，4k@60fps的H.264 解码器和4K@60fps的AV1解码器；还支持4K@60fps的H.264和H.265编码器。内置3D GPU，能够完全兼容OpenGL ES1.1/2.0/3.2、OpenCL 2.0和Vulkan 1.1。引入了新一代完全基于硬件的最大 16M 像素 ISP（图像信号处理器），实现了多种算法加速器，如HDR、3A、CAC、3DNR、2DNR、锐化、去雾、增强、鱼眼校正、伽马校正等。内嵌的NPU算力高达6TOP，支持INT4/INT8/INT16/FP16混合运算。提供完整的Linux开发包供客户二次开发。
图1 EAI3576-Core-T 正面
图2 EAI3576-Core-T反面
1.2 RK3576资源框图
图 3 RK3576功能框图
1.3 选型对比
表1 核心板选型对比表
| 型号 | EAI3576-Core-T | EAI3576-Core-TI |
|---|---|---|
| 芯片制程 | 8nm | 8nm |
| 处理器 | RK3576 | RK3576J |
| CPU | 八核64位ARM v8处理器，4×A72@2.2GHz+4×A53@1.8GHz + ARM Cortex-M0 MCU及支持NEON指令集 | 八核64位ARM v8处理器，4×A72@2.2GHz+4×A53@1.8GHz + ARM Cortex-M0 MCU及支持NEON指令集 |
| NPU | 支持INT4/INT8/INT16/FP16/BF16/TF32混合运算，算力高达6TOPS | 支持INT4/INT8/INT16/FP16/BF16/TF32混合运算，算力高达6TOPS |
| GPU | G52 MC3 GPU@900MHz，支持OpenGL ES 3.2, 并支持2D RGA加速模块 | G52 MC3 GPU@900MHz，支持OpenGL ES 3.2, 并支持2D RGA加速模块 |
| VPU | 8K@30fps H.264/H.2652 Decoder4K@60fps H.264/H.265 Encoder | 8K@30fps H.264/H.2652 Decoder4K@60fps H.264/H.265 Encoder |
| ISP | 16M ISP with HDR (up to 120dB) | 16M ISP with HDR (up to 120dB) |
| 操作系统 | Debian12/Ubuntu 22.04 | Debain12/Ubuntu 22.04 |
| 内存 | 2/4GB LPDDR4X | 2/4GB LPDDR4X |
| 电子硬盘 | 16/32GB EMMC | 16/32GB EMMC |
| MIPI DSI接口 | 2560x1600@60Hz | 2560x1600@60Hz |
| HDMI/eDP | 1路HDMI 2.1或者eDP1.3， HDMI TX支持最大7680x4320@60Hz输出，eDP支持最大4K@60Hz输出 | 1路HDMI 2.1或者eDP1.3， HDMI TX支持最大7680x4320@60Hz输出，eDP支持最大4K@60Hz输出 |
| BT.1120 | 24bit，分辨率1920x1080@60Hz | 24bit，分辨率1920x1080@60Hz |
| MIPI CSI(DPHY/CPHY) | 2路DPHY/CPHY；MIPI DPHY V1.2，4 lanes，2.5Gbps每Lane；MIPI CPHY V1.1，3 lanes，2.5Gsps每Lane | 2路DPHY/CPHY；MIPI DPHY V1.2，4 lanes，2.5Gbps每Lane；MIPI CPHY V1.1，3 lanes，2.5Gsps每Lane |
| MIPI CSIDPHY | 1路；MIPI DPHY V1.2，4 lanes，2.5Gbps每Lane；可复用位4路2 Lanes MIPI CSI | 1路；MIPI DPHY V1.2，4 lanes，2.5Gbps每Lane；可复用位4路2 Lanes MIPI CSI |
| DVP | 1路8/10/12/16-bit标准DVP接口, 最高150MHz数据输入，支持BT.601/BT.656和BT.1120 | 1路8/10/12/16-bit标准DVP接口, 最高150MHz数据输入，支持BT.601/BT.656和BT.1120 |
| I2S | 3路 | 3路 |
| SPDIF(8ch) | 2路 | 2路 |
| PCIE 2.1 | 2路，与SATA3.0和USB3.1复用 | 2路，与SATA3.0和USB3.1复用 |
| SATA3.0 | 2路，与PCIE2.1和USB3.1复用 | 2路，与PCIE2.1和USB3.1复用 |
| USB3.0 Host | 1路，与SATA3.0和PCIE2.1复用 | 1路，与SATA3.0和PCIE2.1复用 |
| USB2.0 Host | 1路USB2.0 Host | 1路USB2.0 Host |
| USB2.0 OTG | 1路USB 2.0 OTG | 1路USB 2.0 OTG |
| USB3.0 OTG | 1路USB 3.0 OTG | 1路USB 3.0 OTG |
| SDIO 3.0 | 2路 | 2路 |
| 以太网 | 2路千兆 | 2路千兆 |
| I2C | 10路 | 10路 |
| I3C | 2路 | 2路 |
| SPI | 5路 | 5路 |
| UART | 12路（含1路调试串口） | 12路（含1路调试串口） |
| CAN | 2路CANFD 1Mbps | 2路CANFD 1Mbps |
| 供电电压 | 5V | 5V |
| 机械尺寸 | 52mm * 48mm | 52mm * 48mm |
| 对外物理接口 | 连接器80pin *4（0.5mm间距），共320个引脚 | 连接器80pin *4（0.5mm间距），共320个引脚 |
| 环境测试 | -20℃ ~ +85℃ | -40℃ ~ +85℃ |
| 评估套件 | EASY-EAI-Orin-Nano | EASY-EAI-Orin-Nano-I |
2.引脚功能
2.1 引脚信息
EAI3576-Core-T核心板将RK3576处理器引脚复用功能维持原定义、扩展或转换功能重新定义，用户可参考设计，以配合产品标准驱动的开发。为了保证产品设计具有良好的兼容性和稳定性，用户没有使用到的引脚资源务必悬空处理。接口引脚排列顺序实物图示意如图4所示。EAI3576-Core-T共有320个引脚，通过四个板对板连接器引出，连接器是80pin，0.5mm间距，3mm高度。注意: 底板母座型号是DF12NA(3.0)-80DP-0.5V(51)，需要带定位孔的连接器。
图4 引脚接口描述
2.2 模块引脚定义
EAI3576-Core-T接口引脚定义如表2，表3，表4，表5所示。核心板所有引脚功能均按下表的“默认功能”作了规定，请勿轻易修改，否则可能和出厂驱动冲突。如有疑问，请及时联系灵眸科技的技术支持。
表2 连接器A座引脚描述
| 引脚 | 标号 | 输入/输出 | 默认功能描述 | IO电平 | 可复用GPIO | 处理器引脚 |
|---|---|---|---|---|---|---|
| A1 | USB2_HOST1_P | B | USB2 OTG Port1 data Plus | -- | -- | 2T4 |
| A3 | USB2_HOST1_N | B | USB2 OTG Port1 data Minus | -- | -- | 2T5 |
| A5 | GND | -- | -- | -- | -- | |
| A7 | USB2_OTG1_VBUSDET | I | USB2 OTG1 connected vbus power detect,pull-down a 40K resistor internal (Valid voltage range:2.7-3.3V) | 3.3V | -- | 2T10 |
| A9 | USB2_OTG1_ID | I | USB2 OTG1 ID detect(Internal weak pull-up to USB2_OTG_AVDD1V8) | 1.8V | -- | 2T9 |
| A11 | GND | -- | GND | -- | -- | -- |
| A13 | USB2_OTG0_P | B | USB2 OTG Port0 data Plus | -- | -- | AK9 |
| A15 | USB2_OTG0_N | B | USB2 OTG Port0 data Minus | -- | -- | AL9 |
| A17 | GND | -- | GND | -- | -- | -- |
| A19 | USB2_OTG0_ID | I | USB2 OTG0 ID detect(Internal weak pull-up to USB2_OTG_AVDD1V8) | 1.8V | -- | 2R6 |
| A21 | GPIO3_D6 | B | GPIO | 1.8V | GPIO3_D6_d | 1C10 |
| A23 | GND | -- | GND | -- | -- | -- |
| A25 | MIPI_CSI_CAM0_PWREN_H | B | GPIO | 1.8V | GPIO3_D0_d | 1C12 |
| A27 | GPIO4_B2_d | B | GPIO | 3.3V | GPIO4_B2_d | B6 |
| A29 | GPIO4_B0_d | B | GPIO | GPIO4_B0_d | 1A5 | |
| A31 | GND | -- | GND | -- | -- | -- |
| A33 | PWM2_CH6_M0 | B | PWM controller 2 channel 6, iomux on Pin A7 | 3.3V | GPIO4_A7_d | A7 |
| A35 | MIPI_CSI_CAM0_RST_H | B | GPIO | 1.8V | GPIO3_D5_d | 1D10 |
| A37 | GPIO3_D4_d | B | GPIO | 1.8V | GPIO3_D4_d | 1E12 |
| A39 | SPI0_MISO_M0 | B | SPI0 master input,slave output, iomux on Pin AC28 | 3.3V | GPIO0_D1_d | AC28 |
| A41 | GND | -- | GND | -- | -- | -- |
| A43 | GPIO0_B0_z | B | GPIO | 1.8V | GPIO0_B0_z | 1U22 |
| A45 | GPIO0_B1_z | B | GPIO | 1.8V | GPIO0_B1_z | 1P23 |
| A47 | GPIO1_D4_d | B | GPIO | 1.8V | GPIO1_D4_d | 1E21 |
| A49 | SDMMC1_DETN_M0 | I | SDMMC1 detect input, iomux on Pin 1C23 | 1.8V | GPIO1_C3_u | 1C23 |
| A51 | GPIO1_C5_d | B | GPIO | 1.8V | GPIO1_C5_d | B28 |
| A53 | GPIO1_C2_u | B | GPIO | 1.8V | GPIO1_C2_u | B29 |
| A55 | I2C8_SCL_M1 | B | I2C8 bus clock, iomux on Pin A26 | 1.8V | GPIO1_C6_d | A26 |
| A57 | I2C8_SDA_M1 | B | I2C8 bus data/adress, iomux on Pin 1C22 | 1.8V | GPIO1_C7_d | 1C22 |
| A59 | GPIO1_C4_d | B | GPIO | 1.8V | GPIO1_C4_d | 1B23 |
| A61 | GND | -- | GND | -- | -- | -- |
| A63 | PCIE0_REFCLK_P | B | PCIe0 differential clock positive, input or output | -- | -- | 1N22 |
| A65 | PCIE0_REFCLK_N | B | PCIe0 differential clock negative,input or output | -- | -- | 1N23 |
| A67 | GND | -- | GND | -- | -- | -- |
| A69 | USB3_HOST1_SSTX_P | O | USB30 OTG Port1 transmit differential positive | -- | -- | N28 |
| A71 | USB3_HOST1_SSTX_N | O | USB30 OTG Port1 transmit differential negative | -- | -- | N29 |
| A73 | GND | -- | GND | -- | -- | -- |
| A75 | USB3_HOST1_SSRX_P | I | USB30 OTG Port1 receive differential positive | -- | -- | M28 |
| A77 | USB3_HOST1_SSRX_N | I | USB30 OTG Port1 receive differential negative | -- | -- | M29 |
| A79 | GND | -- | GND | -- | -- | -- |
| A2 | MIPI_CSI_CAM1_CLKOUT | O | Camera1 master clock output, iomux on Pin 1B12 | 1.8V | GPIO4_A0_d | 1B12 |
| A4 | GND | -- | GND | -- | -- | -- |
| A6 | MIPI_CSI_CAM0_CLKOUT | O | Camera0 master clock output, iomux on Pin 1E7 | 1.8V | GPIO3_D7_d | 1E7 |
| A8 | GND | -- | GND | -- | -- | -- |
| A10 | SAI0_MCLK_M0 | B | SAI0 master clock, iomux on Pin 1C18 | 3.3V | GPIO2_B5_d | 1C18 |
| A12 | MIPI_CSI_CAM1_PDN_H | B | GPIO | 1.8V | GPIO3_B0_d | B14 |
| A14 | GPIO4_A1_d | B | GPIO | 1.8V | GPIO4_A1_d | 1B7 |
| A16 | MIPI_CSI_CAM0_PDN_H | B | GPIO | 1.8V | GPIO3_C7_d | 1C7 |
| A18 | MIPI_CSI_CAM1_PWREN_H | B | GPIO | 1.8V | GPIO3_C5_d | 1B9 |
| A20 | USB2_OTG0_VBUSDET | I | USB2 OTG0 connected vbus power detect,pull-down a 40K resistor internal (Valid voltage range:2.7-3.3V) | 3.3V | -- | 2P3 |
| A22 | GND | -- | GND | -- | -- | -- |
| A24 | CAN0_TX_M2 | O | CAN0 transmit data, iomux on Pin 1C5 | 3.3V | GPIO4_A4_d | 1C5 |
| A26 | CAN0_RX_M2 | I | CAN0 receive data, iomux on Pin 1B5 | 3.3V | GPIO4_A6_d | 1B5 |
| A28 | GND | -- | GND | -- | -- | -- |
| A30 | I2C3_SDA_M0_AUDIO | B | I2C3 bus data/address, iomux on Pin B8 | 3.3V | GPIO4_B4_d | B8 |
| A32 | I2C3_SCL_M0_AUDIO | B | I2C3 bus clock, iomux on Pin 1A4 | 3.3V | GPIO4_B5_d | 1A4 |
| A34 | GND | -- | GND | -- | -- | -- |
| A36 | SAI1_LRCK_M0 | B | SAI1 left/right channel clock(Default for Play and Record), iomux on Pin 1B6 | 3.3V | GPIO4_A5_d | 1B6 |
| A38 | SAI1_SCLK_M0 | B | SAI1 serial clock or Bclock(Default for Play and Record), iomux on Pin 1C6 | 3.3V | GPIO4_A3_d | 1C6 |
| A40 | SAI1_MCLK_M0 | B | SAI1 master clock, iomux on Pin 1D6 | 3.3V | GPIO4_A2_d | 1D6 |
| A42 | SAI1_SDO2_M0 | O | SAI1 data 2 output, iomux on Pin B7 | 3.3V | GPIO4_B1_d | B7 |
| A44 | SAI1_SDI0_M0 | I | SAI1 data 0 input, iomux on Pin 1A6 | 3.3V | GPIO4_B3_d | 1A6 |
| A46 | GND | -- | GND | -- | -- | -- |
| A48 | SDMMC1_D0_M0 | B | SDMMC1 data 0, iomux on Pin A28 | 1.8V | GPIO1_B4_d | A28 |
| A50 | SDMMC1_D1_M0 | B | SDMMC1 data 1, iomux on Pin B27 | 1.8V | GPIO1_B5_d | B27 |
| A52 | SDMMC1_D2_M0 | B | SDMMC1 data 2, iomux on Pin 1A23 | 1.8V | GPIO1_B6_d | 1A23 |
| A54 | SDMMC1_D3_M0 | B | SDMMC1 data 3, iomux on Pin A27 | 1.8V | GPIO1_B7_d | A27 |
| A56 | SDMMC1_CMD_M0 | B | SDMMC1 command, iomux on Pin B26 | 1.8V | GPIO1_C0_d | B26 |
| A58 | GND | -- | GND | -- | -- | -- |
| A60 | SDMMC1_CLK_M0 | O | SDMMC1 clock, iomux on Pin 1B22 | 1.8V | GPIO1_C1_d | 1B22 |
| A62 | GND | -- | GND | -- | -- | -- |
| A64 | PCIE1_REFCLKP | B | PCIe1 differential clock positive, input or output | -- | -- | 1L23 |
| A66 | PCIE1_REFCLKN | B | PCIe1 differential clock negative,input or output | -- | -- | 1M23 |
| A68 | GND | -- | GND | -- | -- | -- |
| A70 | PCIE0_TX_P | O | PCIe0 transmit differential positive | -- | -- | P29 |
| A72 | PCIE0_TX_N | O | PCIe0 transmit differential negative | -- | -- | P28 |
| A74 | GND | -- | GND | -- | -- | -- |
| A76 | PCIE0_RX_P | I | PCIe0 receive differential positive | -- | -- | R28 |
| A78 | PCIE0_RX_N | I | PCIe0 receive differential negative | -- | -- | R29 |
| A80 | GND | -- | GND | -- | -- | -- |
表3 连接器B座引脚描述
| 引脚 | 标号 | 输入/输出 | 默认功能描述 | IO电平 | 可复用GPIO | 处理器引脚 |
|---|---|---|---|---|---|---|
| B1 | GMAC0_TXCLK_M0 | B | GPIO | 1.8V | GPIO3_B6_d | B11 |
| B3 | GND | -- | GND | -- | -- | -- |
| B5 | GMAC0_TXCTL_M0 | O | GMAC0 transmit controller signal, iomux on Pin A11 | 1.8V | GPIO3_B3_d | A11 |
| B7 | GMAC0_TXD0_M0 | O | GMAC0 transmit data 0, iomux on Pin 1A9 | 1.8V | GPIO3_B5_d | 1A9 |
| B9 | GMAC0_TXD3_M0 | O | GMAC0 transmit data 3, iomux on Pin B9 | 1.8V | GPIO3_C2_d | B9 |
| B11 | GMAC0_TXD1_M0 | O | GMAC0 transmit data 1, iomux on Pin B10 | 1.8V | GPIO3_B4_d | B10 |
| B13 | GMAC0_TXD2_M0 | O | GMAC0 transmit data 2, iomux on Pin 1A8 | 1.8V | GPIO3_C3_d | 1A8 |
| B15 | GND | -- | GND | -- | -- | -- |
| B17 | GMAC0_RXD3_M0 | I | GMAC0 receive data 3, iomux on Pin 1A10 | 1.8V | GPIO3_D2_d | 1A10 |
| B19 | GMAC0_RXD2_M0 | I | GMAC0 receive data 2, iomux on Pin B12 | 1.8V | GPIO3_D3_d | B12 |
| B21 | GMAC0_RXD1_M0 | I | GMAC0 receive data 1, iomux on Pin 1A11 | 1.8V | GPIO3_B1_d | 1A11 |
| B23 | GMAC0_RXD0_M0 | I | GMAC0 receive data 0, iomux on Pin A13 | 1.8V | GPIO3_B2_d | A13 |
| B25 | GMAC0_RXCTL_M0 | I | GMAC0 receive data valid/carrier sense, iomux on Pin B13 | 1.8V | GPIO3_A7_d | B13 |
| B27 | GND | -- | GND | -- | -- | -- |
| B29 | GMAC0_RXCLK_M0 | I | GMAC0 receive clock, iomux on Pin 1A12 | 1.8V | GPIO3_D1_d | 1A12 |
| B31 | GND | -- | GND | -- | -- | -- |
| B33 | SAI0_SDO2_M0 | O | SAI0 data 2 output, iomux on Pin 1B16 | 3.3V | GPIO2_B3_d | 1B16 |
| B35 | GND | -- | GND | -- | -- | -- |
| B37 | GMAC0_MDIO_M0 | B | GAMC0 management data, iomux on Pin A9 | 1.8V | GPIO3_A5_d | A9 |
| B39 | GMAC0_MDC_M0 | O | GMAC0 management data clock, iomux on Pin 1A7 | 1.8V | GPIO3_A6_d | 1A7 |
| B41 | GND | -- | GND | -- | -- | -- |
| B43 | ETH_CLK1_25M_OUT_M0 | O | CPU output clock 25MHz for Ethernet PHY1, iomux on Pin 1D18 | 3.3V | GPIO2_D6_d | 1D18 |
| B45 | GND | -- | GND | -- | -- | -- |
| B47 | GPIO3_C6_d | B | GPIO | 1.8V | GPIO3_C6_d | 1D7 |
| B49 | UART10_TX_M1 | O | UART10 transmit data, iomux on Pin C29 | 1.8V | GPIO1_D0_d | C29 |
| B51 | GPIO1_D2_d | B | GPIO | 1.8V | GPIO1_D2_d | 1A24 |
| B53 | I2C4_SDA_M3_MIPI_CAM0 | B | I2C4 bus data/adress, iomux on Pin 1D12 | 1.8V | GPIO3_B7_d | 1D12 |
| B55 | I2C4_SCL_M3_MIPI_CAM0 | B | I2C4 bus clock, iomux on Pin 1E9 | 1.8V | GPIO3_C0_d | 1E9 |
| B57 | I2C5_SDA_M3_MIPI_CAM1 | B | I2C5 bus data/adress, iomux on Pin 1B10 | 1.8V | GPIO3_C1_d | 1B10 |
| B59 | I2C5_SCL_M3_MIPI_CAM1 | B | I2C5 bus clock, iomux on Pin 1D9 | 1.8V | GPIO3_C4_d | 1D9 |
| B61 | GND | -- | GND | -- | -- | -- |
| B63 | TYPEC_DP_AUX_PUPDCTL1 | I | DP Hot Plug detection interrupt, iomux on Pin AL3 | 3.3V | GPIO4_C4_d | AL3 |
| B65 | HDMI_TX_CEC_M0 | B | HDMI TX CEC, iomux on Pin AK3 | 3.3V | GPIO4_C0_d | AK3 |
| B67 | PWM2_CH3_M1 | B | PWM controller 2 channel 3, iomux on Pin AJ1 | 3.3V | GPIO4_C7_d | AJ1 |
| B69 | HDMI_TX_ON_H | B | GPIO | 3.3V | GPIO4_C6_d | 1AE1 |
| B71 | HDMI_TX_SCL | B | HDMI TX I2C bus clock | 3.3V | GPIO4_C2_d | AL2 |
| B73 | HDMI_TX_SDA | B | HDMI TX I2C bus data/address | 3.3V | GPIO4_C3_d | 1AE2 |
| B75 | SPI3_MOSI_M0 | B | SPI3 master output,slave input, iomux on Pin 1B18 | 3.3V | GPIO3_A1_d | 1B18 |
| B77 | SPI3_CLK_M0 | B | SPI3 clock, iomux on Pin 1D16 | 3.3V | GPIO3_A0_d | 1D16 |
| B79 | SPI3_MISO_M0 | B | SPI3 master input,slave output, iomux on Pin 1A20 | 3.3V | GPIO3_A2_d | 1A20 |
| B2 | GMAC1_TXCLK_M0 | O | GMAC1 transmit clock, iomux on Pin 1C15 | 3.3V | GPIO2_C5_d | 1C15 |
| B4 | GND | -- | GND | -- | -- | -- |
| B6 | GMAC1_TXD3_M0 | O | GMAC1 transmit data 3, iomux on Pin 1A13 | 3.3V | GPIO2_C4_d | 1A13 |
| B8 | GMAC1_TXD2_M0 | O | GMAC1 transmit data 2, iomux on Pin A15 | 3.3V | GPIO2_C3_d | A15 |
| B10 | GMAC1_TXD1_M0 | O | GMAC1 transmit data 1, iomux on Pin B15 | 3.3V | GPIO2_C7_d | B15 |
| B12 | GMAC1_TXD0_M0 | O | GMAC1 transmit data 0, iomux on Pin 1A14 | 3.3V | GPIO2_C6_d | 1A14 |
| B14 | GMAC1_TXCTL_M0 | O | GMAC1 transmit controller signal, iomux on Pin B16 | 3.3V | GPIO2_D0_d | B16 |
| B16 | GND | -- | GND | -- | -- | -- |
| B18 | GMAC1_RXCLK_M0 | I | GMAC1 receive clock, iomux on Pin 1D15 | 3.3V | GPIO2_C2_d | 1D15 |
| B20 | GND | -- | GND | -- | -- | -- |
| B22 | GMAC1_RXCTL_M0 | I | GMAC1 receive data valid/carrier sense, iomux on Pin B18 | 3.3V | GPIO2_D3_d | B18 |
| B24 | GMAC1_RXD0_M0 | I | GMAC1 receive data 0, iomux on Pin 1A16 | 3.3V | GPIO2_D1_d | 1A16 |
| B26 | GMAC1_RXD1_M0 | I | GMAC1 receive data 1, iomux on Pin B17 | 3.3V | GPIO2_D2_d | B17 |
| B28 | GMAC1_RXD2_M0 | I | GMAC1 receive data 2, iomux on Pin A17 | 3.3V | GPIO2_C0_d | A17 |
| B30 | GMAC1_RXD3_M0 | I | GMAC1 receive data 3, iomux on Pin 1A15 | 3.3V | GPIO2_C1_d | 1A15 |
| B32 | GND | -- | GND | -- | -- | -- |
| B34 | SAI0_SDI0_M0 | I | SAI0 data 0 input, iomux on Pin B19 | 3.3V | GPIO2_B0_d | B19 |
| B36 | GMAC1_MDIO_M0 | B | GAMC1 management data, iomux on Pin 1B15 | 3.3V | GPIO2_D5_d | 1B15 |
| B38 | GMAC1_MDC_M0 | O | GMAC1 management data clock, iomux on Pin 1B13 | 3.3V | GPIO2_D4_d | 1B13 |
| B40 | GND | -- | GND | -- | -- | -- |
| B42 | WIFI_WAKE_HOST | B | GPIO | 3.3V | GPIO0_B0_z | 1U22 |
| B44 | UART8_TX_M1 | O | UART8 transmit data, iomux on Pin B22 | 3.3V | GPIO2_A6_d | B22 |
| B46 | GND | -- | GND | -- | -- | -- |
| B48 | ETH_CLK0_25M_OUT_M0 | O | CPU output clock 25MHz for Ethernet PHY0, iomux on Pin 1D13 | 1.8V | GPIO3_A4_d | 1D13 |
| B50 | GND | -- | GND | -- | -- | -- |
| B52 | UART10_RX_M1 | I | UART10 receive data, iomux on Pin 1D22 | 1.8V | GPIO1_D1_d | 1D22 |
| B54 | UART8_RX_M1 | I | UART8 receive data, iomux on Pin B20 | 3.3V | GPIO2_A7_d | B20 |
| B56 | GPIO1_D3_d | B | GPIO | 1.8V | GPIO1_D3_d | C28 |
| B58 | GND | -- | GND | -- | -- | -- |
| B60 | GPIO1_D5_d | B | GPIO | 1.8V | GPIO1_D5_d | 1E22 |
| B62 | SPI3_CSN0_M0 | B | SPI3 chip select 0, iomux on Pin 1A19 | 3.3V | GPIO3_A3_d | 1A19 |
| B64 | TYPEC_DP_AUX_PUPDCTL2 | B | GPIO | 3.3V | GPIO4_C5_d | AK1 |
| B66 | HDMI_TX_HPDIN_M0 | I | HDMI Hot Plug detection interrupt, iomux on Pin AK2 | 3.3V | GPIO4_C1_d | AK2 |
| B68 | GND | -- | GND | -- | -- | -- |
| B70 | DP_TX_AUX_P | B | DP AUX differential data positive | -- | -- | 2T2 |
| B72 | DP_TX_AUX_N | B | DP AUX differential data negative | -- | -- | 2T3 |
| B74 | GND | -- | GND | -- | -- | -- |
| B76 | MIPI_DPHY_CSI2_RX_CLKN | -- | MIPI DPHY CSI2 receive differential clock negative | -- | -- | 1AD22 |
| B78 | MIPI_DPHY_CSI2_RX_CLKP | I | MIPI DPHY CSI2 receive differential clock positive | -- | -- | 1AD21 |
| B80 | GND | -- | GND | -- | -- | -- |
表4 连接器C座引脚描述
| 引脚 | 标号 | 输入/输出 | 默认功能描述 | IO电平 | 可复用GPIO | 处理器引脚 |
|---|---|---|---|---|---|---|
| C1 | GND | -- | GND | -- | -- | -- |
| C3 | MIPI_CSI0_RX_D2_N | I | MIPI DPHY CSI0 receive differential data lane 2 negative | -- | -- | AL23 |
| C5 | MIPI_CSI0_RX_D2_P | I | MIPI DPHY CSI0 receive differential data lane 2 positive | -- | -- | AK23 |
| C7 | MIPI_CSI0_RX_D3_N | I | MIPI DPHY CSI0 receive differential data lane 3 negative | -- | -- | AL24 |
| C9 | MIPI_CSI0_RX_D3_P | I | MIPI DPHY CSI0 receive differential data lane 3 positive | -- | -- | AK24 |
| C11 | MIPI_CSI0_RX_D1_N | I | MIPI DPHY CSI0 receive differential data lane 1 negative | -- | -- | AL21 |
| C13 | MIPI_CSI0_RX_D1_P | I | MIPI DPHY CSI0 receive differential data lane 1 positive | -- | -- | AK21 |
| C15 | GND | -- | GND | -- | -- | -- |
| C17 | MIPI_CSI0_RX_CLK_N | I | MIPI DPHY CSI0 receive differential clock negative | -- | -- | AL22 |
| C19 | MIPI_CSI0_RX_CLK_P | I | MIPI DPHY CSI0 receive differential clock positive | -- | -- | AK22 |
| C21 | GND | -- | GND | -- | -- | -- |
| C23 | MIPI_CSI0_RX_D0_N | I | MIPI DPHY CSI0 receive differential data lane 0 negative | -- | -- | AL20 |
| C25 | MIPI_CSI0_RX_D0_P | I | MIPI DPHY CSI0 receive differential data lane 0 positive | -- | -- | AK20 |
| C27 | USB3_OTG0_SSRX2_P | I | USB3 OTG Port0 receive differential data lane 2 positive | -- | -- | AK12 |
| C29 | USB3_OTG0_SSRX2_N | I | USB3 OTG Port0 receive differential data lane 2 negative | -- | -- | AL12 |
| C31 | GND | -- | GND | -- | -- | -- |
| C33 | USB3_OTG0_SSTX2_P | O | USB3 OTG Port0 transmit differential data lane 2 positive | -- | -- | AL13 |
| C35 | USB3_OTG0_SSTX2_N | O | USB3 OTG Port0 transmit differential data lane 2 negative | -- | -- | AK13 |
| C37 | GND | -- | GND | -- | -- | -- |
| C39 | USB3_OTG0_SSRX1_P | I | USB3 OTG Port0 receive differential data lane 1 positive | -- | -- | AK10 |
| C41 | USB3_OTG0_SSRX1_N | I | USB3 OTG Port0 receive differential data lane 1 negative | -- | -- | AL10 |
| C43 | GND | -- | GND | -- | -- | -- |
| C45 | USB3_OTG0_SSTX1_P | O | USB3 OTG Port0 transmit differential data lane 1 positive | -- | -- | AL11 |
| C47 | USB3_OTG0_SSTX1_N | O | USB3 OTG Port0 transmit differential data lane 1 negative | -- | -- | AK11 |
| C49 | GND | -- | GND | -- | -- | -- |
| C51 | MIPI_DPHY_CSI3_RX_D2N | I | MIPI DPHY CSI3 receive differential data lane 2 negative | -- | -- | K29 |
| C53 | MIPI_DPHY_CSI3_RX_D2P | I | MIPI DPHY CSI3 receive differential data lane 2 positive | -- | -- | K28 |
| C55 | MIPI_DPHY_CSI3_RX_D0N | I | MIPI DPHY CSI3 receive differential data lane 0 negative | -- | -- | H29 |
| C57 | MIPI_DPHY_CSI3_RX_D0P | I | MIPI DPHY CSI3 receive differential data lane 0 positive | -- | -- | H28 |
| C59 | MIPI_DPHY_CSI3_RX_D1N | I | MIPI DPHY CSI3 receive differential data lane 1 negative | -- | -- | J29 |
| C61 | MIPI_DPHY_CSI3_RX_D1P | I | MIPI DPHY CSI3 receive differential data lane 1 positive | -- | -- | J28 |
| C63 | MIPI_DPHY_CSI3_RX_D3N | I | MIPI DPHY CSI3 receive differential data lane 3 negative | -- | -- | L29 |
| C65 | MIPI_DPHY_CSI3_RX_D3P | I | MIPI DPHY CSI3 receive differential data lane 3 positive | -- | -- | L28 |
| C67 | GND | -- | GND | -- | -- | -- |
| C69 | MIPI_DPHY_CSI3_RX_CLKN | I | MIPI DPHY CSI3 receive differential clock negative | -- | -- | 1H23 |
| C71 | MIPI_DPHY_CSI3_RX_CLKP | I | MIPI DPHY CSI3 receive differential clock positive | -- | -- | 1H22 |
| C73 | GND | -- | GND | -- | -- | -- |
| C75 | MIPI_DPHY_CSI4_RX_CLKN | I | MIPI DPHY CSI4 receive differential clock negative | -- | -- | 1K23 |
| C77 | MIPI_DPHY_CSI4_RX_CLKP | I | MIPI DPHY CSI4 receive differential clock positive | -- | -- | 1K22 |
| C79 | GND | -- | GND | -- | -- | -- |
| C2 | GND | -- | GND | -- | -- | -- |
| C4 | HDMI_TX_SBD_P | B | HDMI sideband differential data lane positive | -- | -- | 2T12 |
| C6 | HDMI_TX_SBD_N | B | HDMI sideband differential data lane Nesitive | -- | -- | 2U12 |
| C8 | GND | -- | GND | -- | -- | -- |
| C10 | HDMI_TX_D0_P | O | HDMI transmit differential data lane 0 positive | -- | -- | 1AE24 |
| C12 | HDMI_TX_D0_N | O | HDMI transmit differential data lane 0 negative | -- | -- | AK27 |
| C14 | GND | -- | GND | -- | -- | -- |
| C16 | HDMI_TX_D1_P | O | HDMI transmit differential data lane 1 positive | -- | -- | AK28 |
| C18 | HDMI_TX_D1_N | O | HDMI transmit differential data lane 1 negative | -- | -- | AL28 |
| C20 | GND | -- | GND | -- | -- | -- |
| C22 | HDMI_TX_D2_P | O | HDMI transmit differential data lane 2 positive | -- | -- | AJ28 |
| C24 | HDMI_TX_D2_N | O | HDMI transmit differential data lane 2 negative | -- | -- | AK29 |
| C26 | GND | -- | GND | -- | -- | -- |
| C28 | HDMI_TX_D3_P | O | HDMI transmit differential data lane 3 positive | -- | -- | AL26 |
| C30 | HDMI_TX_D3_N | O | HDMI transmit differential data lane 3 negative | -- | -- | AK26 |
| C32 | GND | -- | GND | -- | -- | -- |
| C34 | MIPI_DPHY_DSI_TX_CLK_N | O | MIPI DPHY transmit differential clock negative | -- | -- | AK17 |
| C36 | MIPI_DPHY_DSI_TX_CLK_P | O | MIPI DPHY transmit differential clock positive | -- | -- | AL17 |
| C38 | GND | -- | GND | -- | -- | -- |
| C40 | MIPI_DSI_TX_D0_N | O | MIPI DPHY transmit differential data lane 0 negative | -- | -- | AK15 |
| C42 | MIPI_DSI_TX_D0_P | O | MIPI DPHY transmit differential data lane 0 positive | -- | -- | AL15 |
| C44 | MIPI_DSI_TX_D1_N | O | MIPI DPHY transmit differential data lane 1 negative | -- | -- | AK16 |
| C46 | MIPI_DSI_TX_D1_P | O | MIPI DPHY transmit differential data lane 1 positive | -- | -- | AL16 |
| C48 | MIPI_DSI_TX_D2_N | O | MIPI DPHY transmit differential data lane 2 negative | -- | -- | AK18 |
| C50 | MIPI_DSI_TX_D2_P | O | MIPI DPHY transmit differential data lane 2 positive | -- | -- | AL18 |
| C52 | MIPI_DSI_TX_D3_N | O | MIPI DPHY transmit differential data lane 3 negative | -- | -- | AK19 |
| C54 | MIPI_DSI_TX_D3_P | O | MIPI DPHY transmit differential data lane 3 positive | -- | -- | AL19 |
| C56 | GND | -- | GND | -- | -- | -- |
| C58 | MIPI_CSI1_RX_CLK_N | I | MIPI DPHY CSI1 receive differential clock negative | -- | -- | 1AC23 |
| C60 | MIPI_CSI1_RX_CLK_P | I | MIPI DPHY CSI1 receive differential clock positive | -- | -- | 1AC22 |
| C62 | GND | -- | GND | -- | -- | -- |
| C64 | MIPI_CSI1_RX_D0_N | I | MIPI DPHY CSI1 receive differential data lane 0 negative | -- | -- | AE28 |
| C66 | MIPI_CSI1_RX_D0_P | I | MIPI DPHY CSI1 receive differential data lane 0 positive | -- | -- | AE29 |
| C68 | MIPI_CSI1_RX_D1_N | I | MIPI DPHY CSI1 receive differential data lane 1 negative | -- | -- | AF28 |
| C70 | MIPI_CSI1_RX_D1_P | I | MIPI DPHY CSI1 receive differential data lane 1 positive | -- | -- | AF29 |
| C72 | MIPI_CSI1_RX_D2_N | I | MIPI DPHY CSI1 receive differential data lane 2 negative | -- | -- | AG28 |
| C74 | MIPI_CSI1_RX_D2_P | I | MIPI DPHY CSI1 receive differential data lane 2 positive | -- | -- | AG29 |
| C76 | MIPI_CSI1_RX_D3_N | I | MIPI DPHY CSI1 receive differential data lane 3 negative | -- | -- | AH28 |
| C78 | MIPI_CSI1_RX_D3_P | I | MIPI DPHY CSI1 receive differential data lane 3 positive | -- | -- | AH29 |
| C80 | GND | -- | GND | -- | -- | -- |
表5 连接器D座引脚描述
| 引脚 | 标号 | 输入/输出 | 默认功能描述 | IO电平 | 可复用GPIO | 处理器引脚 |
|---|---|---|---|---|---|---|
| D1 | HP_DET | B | GPIO | 3.3V | GPIO0_C5_d | 1AA22 |
| D3 | PCIE0_PWREN_H | B | GPIO | 3.3V | GPIO0_D3_d | 1AA23 |
| D5 | SPI0_CLK_M0 | B | SPI0 clock, iomux on Pin 1Y23 | 3.3V | GPIO0_C7_d | 1Y23 |
| D7 | PCIE0_WAKEN_M0 | B | GPIO | 3.3V | GPIO0_D2_d | 1Y22 |
| D9 | SPI0_CSN0_M0 | B | SPI0 chip select 0, iomux on Pin 1Y21 | 3.3V | GPIO0_C6_d | 1Y21 |
| D11 | PWM0_CH0_M0 | B | PWM controller 0 channel 0, iomux on Pin 1W22 | 3.3V | GPIO0_C4_d | 1W22 |
| D13 | SPI0_MOSI_M0 | B | SPI0 master output,slave input, iomux on Pin 1W23 | 3.3V | GPIO0_D0_d | 1W23 |
| D15 | GPIO0_A2_d | B | GPIO | 1.8V | GPIO0_A2_d | 1U23 |
| D17 | GPIO0_A7_u | B | GPIO | 1.8V | GPIO0_A7_u | 1U21 |
| D19 | SDMMC0_PWREN_H | O | SDMMC0 power enable | 3.3V | GPIO0_B6_d | 1Y24 |
| D21 | GND | -- | GND | -- | -- | -- |
| D23 | UART0_TX_M0_DEBUG | O | UART0 transmit data, iomux on Pin 1U24 | 3.3V | GPIO0_D4_u | 1U24 |
| D25 | UART0_RX_M0_DEBUG | I | UART0 receive data, iomux on Pin AA28 | 3.3V | GPIO0_D5_u | AA28 |
| D27 | SPI3_CSN1_M0 | O | SPI3 chip select 1, iomux on Pin 1E15 | 3.3V | GPIO2_D7_d | 1E15 |
| D29 | GND | -- | GND | -- | -- | -- |
| D31 | PCIE0_PERSTN | B | GPIO | 3.3V | GPIO2_B1_d | 1A18 |
| D33 | GND | -- | GND | -- | -- | -- |
| D35 | PCIE0_CLKREQN_M0 | B | PCIe0 reference clock request, iomux on Pin 1A17 | 3.3V | GPIO2_B2_d | 1A17 |
| D37 | GND | -- | GND | -- | -- | -- |
| D39 | SDMMC0_CLK | O | SDMMC0 clock | 3.3V | GPIO2_A5_d | 1B21 |
| D41 | GND | -- | GND | -- | -- | -- |
| D43 | SDMMC0_D3 | B | SDMMC0 data 3 | 3.3V | GPIO2_A3_d | B23 |
| D45 | SDMMC0_D2 | B | SDMMC0 data 2 | 3.3V | GPIO2_A2_d | A23 |
| D47 | SDMMC0_D1 | B | SDMMC0 data 1 | 3.3V | GPIO2_A1_d | B25 |
| D49 | SDMMC0_D0 | B | SDMMC0 data 0 | 3.3V | GPIO2_A0_d | B24 |
| D51 | SDMMC0_CMD | B | SDMMC0 command | 3.3V | GPIO2_A4_d | 1A21 |
| D53 | GND | -- | GND | -- | -- | -- |
| D55 | GND | -- | GND | -- | -- | -- |
| D57 | GND | -- | GND | -- | -- | -- |
| D59 | GND | -- | GND | -- | -- | -- |
| D61 | GND | -- | GND | -- | -- | -- |
| D63 | GND | -- | GND | -- | -- | -- |
| D65 | GND | -- | GND | -- | -- | -- |
| D67 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D69 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D71 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D73 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D75 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D77 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D79 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D2 | RESET_L | I | System reset input | 1.8V | -- | W28 |
| D4 | GND | -- | GND | -- | -- | -- |
| D6 | PWRON_L | -- | PWRON_L | -- | -- | -- |
| D8 | UART4_TX_M2 | O | UART4 transmit data, iomux on Pin AD28 | 3.3V | GPIO0_B4_d | AD28 |
| D10 | GND | -- | GND | -- | -- | -- |
| D12 | UART4_RX_M2 | I | UART4 receive data, iomux on Pin AD29 | 3.3V | GPIO0_B5_d | AD29 |
| D14 | GND | -- | GND | -- | -- | -- |
| D16 | I2C2_SCL_M0 | B | I2C2 bus clock, iomux on Pin 1W24 | 3.3V | GPIO0_B7_d | 1W24 |
| D18 | I2C2_SDA_M0 | B | I2C2 bus data/adress, iomux on Pin AB29 | 3.3V | GPIO0_C0_d | AB29 |
| D20 | GND | -- | GND | -- | -- | -- |
| D22 | I2C0_SCL_M1_TP | B | I2C0 bus clock, iomux on Pin AB28 | 3.3V | GPIO0_C1_d | AB28 |
| D24 | I2C0_SDA_M1_TP | B | I2C0 bus data/adress, iomux on Pin 1V24 | 3.3V | GPIO0_C2_d | 1V24 |
| D26 | GND | -- | GND | -- | -- | -- |
| D28 | GPIO0_A5_d | B | GPIO | 1.8V | GPIO0_A5_d | Y29 |
| D30 | GPIO0_A0_d | B | GPIO | 1.8V | GPIO0_A0_d | V29 |
| D32 | SARADC_VIN4 | I | SAR ADC channel 4 input | 1.8V | -- | 1E18 |
| D34 | SARADC_VIN3_HP_HOOK | I | SAR ADC channel 3 input | 1.8V | -- | 1C19 |
| D36 | SARADC_VIN5 | I | SAR ADC channel 5 input | 1.8V | -- | 1D19 |
| D38 | SARADC_VIN6 | I | SAR ADC channel 6 input | 1.8V | -- | 1D21 |
| D40 | SARADC_VIN2_HW_ID | I | SAR ADC channel 2 input | 1.8V | -- | 1B19 |
| D42 | SPI0_CSN1_M0 | O | SPI0 chip select 1, iomux on Pin 1W21 | 3.3V | GPIO0_C3_d | 1W21 |
| D44 | SAI0_LRCK_M0 | B | SAI0 left/right channel clock(Default for Play and Record), iomux on Pin B21 | 3.3V | GPIO2_B7_d | B21 |
| D46 | GND | -- | GND | -- | -- | -- |
| D48 | SARADC_VIN0_BOOT | I | SAR ADC channel 0 input,with BOOT | 1.8V | -- | A25 |
| D50 | SARADC_VIN7 | I | SAR ADC channel 7 input | 1.8V | 1E19 | |
| D52 | SARADC_VIN1_RECOVERY | I | SAR ADC channel 1 input,with Recovery | 1.8V | -- | 1A22 |
| D54 | GND | -- | GND | -- | -- | -- |
| D56 | SAI0_SCLK_M0 | B | SAI0 serial clock or Bclock(Default for Play and Record), iomux on Pin A21 | 3.3V | GPIO2_B6_d | A21 |
| D58 | GND | -- | GND | -- | -- | -- |
| D60 | GND | -- | GND | -- | -- | -- |
| D62 | GND | -- | GND | -- | -- | -- |
| D64 | GND | -- | GND | -- | -- | -- |
| D66 | GND | -- | GND | -- | -- | -- |
| D68 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D70 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D72 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D74 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D76 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D78 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
| D80 | VCC5V0_SYS_S5 | I | 5V power supply | -- | -- | -- |
3.电气参数
3.1功耗参数
表6 核心板功耗参数
| 工作条件 | 电源电压 | 电源电流 | 总功耗 | 单位 |
|---|---|---|---|---|
| Linux正常启动 | 5.0V | 0.145A | 0.725W | V/A/W |
| 进入freeze休眠模式 | 5.0V | 0.122A | 0.61W | V/A/W |
| 进入mem休眠模式 | 5.0V | 0.003A | 0.015W | V/A/W |
| CPU占用100%+内存占用20% | 5.0V | 0.862A | 4.31W | V/A/W |
| CPU占用100%+内存占用50% | 5.0V | 0.899A | 4.495W | V/A/W |
| CPU占用100%+内存占用80%+最大算力NPU满载运行 | 5.0V | 1.012A | 5.06W | V/A/W |
3.2 IO电平参数
表7 IO电平（3.3V）
| 参数 | 标号 | 规格 | 说明 | |||
|---|---|---|---|---|---|---|
| 最小 | 典型 | 最大 | 单位 | |||
| 高电平输入电压 | VIH | 2.3 | 3.3 | 3.6 | V | -- |
| 低电平输入电压 | VIL | -0.3 | 0 | 1.0 | V | -- |
| 高电平输出电压 | VOH | 2.64 | 3.3 | -- | V | -- |
| 低电平输出电压 | VOL | -- | 0 | 0.66 | V | -- |
表8 IO电平（1.8V）
| 参数 | 标号 | 规格 | 说明 | |||
|---|---|---|---|---|---|---|
| 最小 | 典型 | 最大 | 单位 | |||
| 高电平输入电压 | VIH | 1.26 | 1.8 | 2.2 | V | -- |
| 低电平输入电压 | VIL | -0.3 | 0 | 0.63 | V | -- |
| 高电平输出电压 | VOH | 1.4 | 1.8 | -- | V | -- |
| 低电平输出电压 | VOL | -- | 0 | 0.4 | V | -- |
4.机械尺寸
表9 核心板机械尺寸
| 参数 | 规格 | 说明 |
|---|---|---|
| 长 | 52mm | -- |
| 宽 | 48mm | -- |
图5 核心板尺寸图-TOP
图6 核心板尺寸图-BOTTOM
5.生产指导
5.1 拆卸注意事项
- 由于核心板BGA元器件比较多，不建议经常插拔。在需要插拔的时候，务必要小心，避免PCB变形造成元件虚焊。
- 由于核心板采用板对板连接器形式接口，将有更好的信号质量，但其使用寿命有限，不建议经常插拔。连接器插拔使用寿命为50次。
- 核心板不可带电插拔，以免造成运行中的DDR、eMMC数据丢失或损坏器件。
- 拆卸时，不能使用尖利的工具拆卸核心板。
5.2 贴片注意事项
核心板的底板板对板连接器生产贴片要满足一定要求，连接器才会良好焊接，推荐钢网厚度0.12mm，开口面积比70%，回流焊或者烙铁焊接都要满足一定的温度条件，具体如图7所示。
图7 连接器焊接和钢网要求图
6. 免责声明
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销售与服务网络
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