ST8500全可编动力线通信调制解调器片上系统

电子工程师 2019-05-01 4592

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描述

　　ST公司的ST8500是全可编动力线通信（PLC）调制解调器片上系统（SoC），采用标准ARM® 32-bit Cortex®-M4F全可编程核，可以运行任何的PLC协议如ITU G.9904（PRIME），ITU G.9903 （G3-PLC®），目标CENELEC EN50065， FCC和ARIB兼容的应用，集成了差分PLC模拟前端，包括具有自动增益控制和PGA和ADC，带发送预驱动器的DAC，数字发送电平控制，零交叉比较器和高达500kHz PLC信号带宽，最高工作频率高达200MHz，工作温度-40℃到+105℃，主要用在智能计量，智能电网和物联网（IoT），以及和CENELEC， FCC 与 ARIB兼容的应用设计。本文介绍了ST8500主要特性，框图和详细架构图以及评估板EVALKITST8500-1主要特性，框图，电路图，材料清单和PCB设计图。

　　The ST8500 is a fully programmable power line communication （PLC） modem System on　Chip （SoC）， able to run any PLC protocol in the frequency band up to 500 kHz.

　　The device architecture has been designed to target CENELEC EN50065， FCC and ARIB　compliant applications supporting all major PLC protocol standards such as ITU G.9904（PRIME）， ITU G.9903 （G3-PLC®） and many other possible PLC protocol specifications andevolutions.

　　ST8500主要特性：

　　 Programmable power line communication（PLC） modem System on Chip

　　 Integrated differential PLC analog front-end

　　– PGA with automatic gain control and ADC

　　– DAC with transmission pre-driver

　　– Digital transmission level control

　　– Zero crossing comparator

　　– Up to 500 kHz PLC signal bandwidth

　　 High performance， fully programmable realtimeengine dedicated to PLC PHY and real -time MAC protocol management （400 MHzmax. frequency）

　　– Dedicated code and data SRAM memories

　　 Standard ARM® 32-bit Cortex®-M4F fullyprogrammable core for protocol upper layers　and peripherals management

　　– 200 MHz maximum frequency

　　– 256 kB of embedded SRAM for code anddata

　　– 96 kB of embedded SRAM for data

　　– 8 kB of embedded shared RAM

　　– Bootloader ROM memory

　　– One Time Programmable （OTP） memorywith dedicated areas available for secure　keys and user information storage

　　– Serial wire and JTAG interfaces

　　– 24 multiplexed GPIOs

　　– 4 general purpose timers

　　– 1 flexible CRC calculation unit

　　– 2 USART， 1 UART， 3 SPI， 1 I2C

　　 Cryptographic engine

　　– AES 128/192/256 engine

　　– True random number generator

　　– Pseudo random number generator

　　 Clock management：

　　– 25 MHz external crystal for system clock

　　– Integrated 25 MHz oscillator （XOSC） withfrequency synthesizer （FS） and　pre-scalerunits to generate internal clock signals

　　 Power management

　　– 3.3 V external supply voltage for I/O andanalog

　　– 2.5 V internal linear regulator for analog

　　– 1.1 V external supply voltage for digital

　　– Normal， Slow， Doze and low power modes

　　 Available in QFN56 package

　　 -40℃ to +105℃ temperature range

　　ST8500应用：

　　 Smart metering， smart grid and Internet ofThings applications

　　 Suitable for application design compliant withCENELEC， FCC and ARIB regulations

调制解调器

　　图1.ST8500基本框图

　　The ST8500 architecture is composed of the following parts：

　　1. PLC front-end including digital front-end （DFE） and analog front-end （AFE）

　　2. Real-time engine： the digital core running the lower layers of the PLC protocol stack　and implementing modulation， demodulation and advanced forward error corrections（FEC） algorithms

　　3. Protocol engine： the digital core running the upper layers of the PLC protocol stack and　managing the interface with external microcontrollers.

　　4. Peripherals， crypto， debug section

　　5. Clock and reset section

　　6. Power management section

调制解调器

　　图1.ST8500详细架构图

　　评估板EVALKITST8500-1

　　The EVALKITST8500-1 is a platform which allows an easy way to evaluate the features andperformance of a power line communication （PLC） node based on the ST8500 modemsystem-on-chip and the STLD1 line driver.

　　This user manual explains the EVALKITST8500-1 hardware and software installation， and　details the evaluation of the kits.

　　This user manual does not explain the functionalities of the various PLC protocols running　on the ST8500. Detailed information can be found in the protocol specific documentation，available within the software packages， separately delivered under the Software license　agreement by contacting your local ST sales office.

调制解调器