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高精度DDFS信号源FPGA实现
消耗积分:5 |
格式:rar |
大小:915 |
2010-12-11
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为进行高精度信号源的设计，同时降低设计成本，以Cyclone II系列低端FPGA为核心，利用直接频率合成技术，对正弦信号等数据进行1/4周期压缩存储到ROM中，在外部时钟频率为50 MHz，实现了正弦信号源的设计，同时，实现三角波、锯齿波、矩形脉冲及2-ASK、2-PSK和2-FSK等数字调制信号，系统还具有扫频、指定波形次数等功能。仿真结果表明，信号源精度高，频率调整步进可达0.034 92 Hz，频率范围为0.034 92 Hz~9.375 MHz，制作成本低，功能丰富。
- Abstract:
- In order to design a high precision signal source and reduce the cost of the design, direct digital frequency synthesis （DDFS） technology is utilized in the low-cost FPGA Cyclone II, and sin function data is stored in ROM of FPGA with the compress rate 1/4 in this design. A high precision DDS signal source is implemented with the 50MHz outside clock frequency based on FPGA. Meanwhile, triangular signal, saw-tooth signal, square signal, plus 2-ASK, 2-PSK and 2-FSK are implemented as well. The system also has the frequency sweep and wave repeat times assignment functions etc. Simulation results show that this signal source has highest frequency 9.375MHz, lowest frequency 0.034 92Hz, and frequency step 0.034 92Hz,it also has the advantages of low manufacture cost and rich function.
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