| Function | Clock divider, Differential |
| Additive RMS jitter (Typ) (fs) | 30 |
| Output frequency (Max) (MHz) | 1600 |
| Number of outputs | 8 |
| Output supply voltage (V) | 3.3 |
| Core supply voltage (V) | 3.3 |
| Output skew (ps) | 30 |
| Features | uWire |
| Operating temperature range (C) | -40 to 85 |
| Rating | Catalog |
| Output type | LVDS |
| Input type | LVDS |
| Device | LVDS | LVPECL |
|---|---|---|
| LMK01000 | 3 | 5 |
| LMK01010 | 8 | 0 |
| LMK01020 | 0 | 8 |
The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.
The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.
Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).
Target Applications