| Function | Clock generator |
| Number of outputs | 1 |
| Output frequency (Max) (MHz) | 156.25 |
| Core supply voltage (V) | 3.3 |
| Output supply voltage (V) | 3.3 |
| Input type | LVCMOS |
| Output type | LVPECL |
| Operating temperature range (C) | -40 to 85 |
| Features | Signal 3.3-V supply, Chip-enable control pin |
| Rating | Catalog |
- Single 3.3-V Supply
- High-Performance Clock Generator, Incorporating Crystal Oscillator Circuitry with Integrated Frequency Synthesizer
- Low Output Jitter: As low as 380 fs (RMS integrated between 10 kHz to 20 MHz)
- Low Phase Noise at 312.5 MHz:
- Less than -120 dBc/Hz at 10 kHz and -147 dBc/Hz at 10-MHz offset from carrier
- Supports Crystal or LVCMOS Input Frequencies at 31.25 MHz, 33.33 MHz, and 35.42 MHz
- Output Frequencies: 100 MHz, 106.25 MHz, 125 MHz, 156.25 MHz, 212.5 MHz, 250 MHz, and 312.5 MHz
- Differential Low-Voltage Positive Emitter Coupled Logic (LVPECL) Outputs
- Fully-Integrated Voltage-Controlled Oscillator (VCO): Runs from 1.75 GHz to 2.35 GHz
- Typical Power Consumption: 300 mW
- Chip Enable Control Pin
- Available in 4-mm × 4-mm QFN-24 Package
- ESD Protection Exceeds 2 kV (HBM)
- Industrial Temperature Range: -40°C to +85°C
- APPLICATIONS
- Low-Cost, Low-Jitter Frequency Multiplier
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The CDC421Axxx is a high-performance, low-phase-noise clock generator. It has an integrated low-noise, LC-based voltage-controlled oscillator (VCO) that operates within the 1.75 GHz to 2.35 GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for a phase-locked loop (PLL)-based frequency synthesizer. The output frequency (fOUT) is proportional to the frequency of the input crystal (fXTAL).
The device operates in 3.3-V supply environment and is characterized for operation from -40°C to +85°C. The CDC421Axxx is available in a QFN-24 4-mm × 4-mm package.
The CDC421Axxx differs from the CDC421xxx in the following ways:
- Device Startup
The CDC421Axxx has an improved startup circuit to enable correct operation for all power-supply ramp times.