| Number of channels (#) | 1 |
| Technology Family | LVC |
| Supply voltage (Min) (V) | 1.65 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock Frequency (Max) (MHz) | 150 |
| IOL (Max) (mA) | 32 |
| IOH (Max) (mA) | -32 |
| ICC (Max) (uA) | 10 |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) |
- Available in the Texas Instruments
NanoFree? Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Supports Down Translation to VCC
- Max tpd of 4.3 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection - Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.