| Number of channels (#) | 1 |
| Technology Family | LVC |
| Supply voltage (Min) (V) | 1.65 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 150 |
| IOL (Max) (mA) | 32 |
| IOH (Max) (mA) | -32 |
| ICC (Max) (uA) | 10 |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff), Flow-through pinout |
- Available in the Texas Instruments
NanoFree? Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Provides Down Translation to VCC
- Max tpd of 4 ns at 3.3 V
- Low Power Consumption: 10-μA
Maximum ICC - ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode and Back Drive Protection
- Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
The SN74LVC1G373 device is a single D-type latch designed for 1.65-V to 5.5-V VCC operation.
This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
NanoFree? package technology is a major breakthrough in IC packaging concepts, using the die as the package.
OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.