| Number of channels (#) | 16 |
| Technology Family | LVT |
| Supply voltage (Min) (V) | 2.7 |
| Supply voltage (Max) (V) | 3.6 |
| Input type | TTL-Compatible CMOS |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 160 |
| IOL (Max) (mA) | 64 |
| IOH (Max) (mA) | -32 |
| ICC (Max) (uA) | 5000 |
| Features | Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Bus-hold, Flow-through pinout |
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources
(DMS) Support - Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Member of the Texas Instruments Widebus? Family
- State-of-the-Art Advanced BiCMOS Technology
(ABT) Design for 3.3-V Operation and Low Static-
Power Dissipation - Supports Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC) - Supports Unregulated Battery Operation Down to
2.7 V - Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C - Ioff and Power-Up Tri-State Support Hot Insertion
- Bus Hold on Data Inputs Eliminates the Need for
External Pullup/Pulldown Resistors - Distributed VCC and GND Pins Minimize High-
Speed Switching Noise - Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per
JESD 17 - ESD Protection Exceeds JESD 22
- 4000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.