| Function | Counter |
| Bits (#) | 4 |
| Technology Family | LV-A |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) |
- 2-V to 5.5-V VCC Operation
- Max tpd of 10 ns at 5 V
- Typical VOLP (Output Ground Bounce)
???<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
???>2.3 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Partial-Power-Down-Mode Operation
- Dual 4-Bit Binary Counters With Individual Clocks
- Direct Clear for Each 4-Bit Counter
- Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The ?LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2-V to 5.5-V VCC operation.
These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)\ input. These devices change state on the negative-going transition of the CLK\ pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ?LV393A devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.