| Number of channels (#) | 6 |
| Technology Family | CD4000 |
| Supply voltage (Min) (V) | 3 |
| Supply voltage (Max) (V) | 18 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Clock Frequency (Max) (MHz) | 8 |
| IOL (Max) (mA) | 6.8 |
| IOH (Max) (mA) | -6.8 |
| ICC (Max) (uA) | 600 |
| Features | Balanced outputs, Standard speed (tpd > 50ns), Positive input clamp diode |
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
????????1 V at VDD = 5 V
????????2 V at VDD = 10 V
?????2.5 V at VDD = 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Shift Registers
- Buffer/Storage Registers
- Pattern Generators
Cd40174B consists of six identical ?D?-type flip-flops having independent DATA inputs. The CLOCK and CLEAR\ inputs are common to all six units. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All sic flip-flops are simultaneously reset by a low level on the CLEAR\ input.
The CD40174B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).