| Number of channels (#) | 20 |
| Technology Family | ALVC |
| Supply voltage (Min) (V) | 1.65 |
| Supply voltage (Max) (V) | 3.6 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 150 |
| IOL (Max) (mA) | 12 |
| IOH (Max) (mA) | -12 |
| ICC (Max) (uA) | 40 |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Damping resistors, Bus-hold |
- Member of the Texas Instruments Widebus? Family
- EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process
- Output Ports Have Equivalent 26-
Series Resistors, So No External Resistors Are Required - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR.
Widebus, EPIC are trademarks of Texas Instruments.
This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCC operation.
The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.
A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.
The SN74ALVCH162721 is characterized for operation from ?40°C to 85°C.