| Number of channels (#) | 2 |
| Technology Family | LVC |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 3.6 |
| Input type | TTL/CMOS |
| Output type | Push-Pull |
| Clock Frequency (MHz) | 150 |
| ICC (Max) (uA) | 10 |
| IOL (Max) (mA) | 24 |
| IOH (Max) (mA) | -24 |
| Features | Balanced outputs, Negative edge triggered, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Preset, Clear |
- Operates From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.8 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C - Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 3000-V Human-Body Model
- 200-V Machine Model
- 1500-V Charged-Device Model
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.