| Number of channels (#) | 8 |
| Technology Family | LVC |
| Supply voltage (Min) (V) | 1.65 |
| Supply voltage (Max) (V) | 3.6 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 100 |
| IOL (Max) (mA) | 24 |
| IOH (Max) (mA) | -24 |
| ICC (Max) (uA) | 10 |
| Features | Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff), Flow-through pinout |
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 6.9 ns at 3.3 V
- Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
- Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
- Latch-Up Performance Exceeds 250 mA
Per JESD 17 - ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
The SN54LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC573A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.