公司logo

华秋商城

1.8w內容 |  99w+浏览量  |  158粉丝

+关注

--- 产品详情 ---

串行输出移位寄存器
Configuration Parallel-in, Serial-out
Bits (#) 8
Technology Family LS
Supply voltage (Min) (V) 4.75
Supply voltage (Max) (V) 5.25
Input type Bipolar
Output type Push-Pull
Clock Frequency (MHz) 25
IOL (Max) (mA) 8
IOH (Max) (mA) -0.4
ICC (Max) (uA) 30000
Features High speed (tpd 10-50ns)
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion

The SN54165 and SN74165 devices are obsolete and are no longer supplied.

The ?165 and ?LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD\) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD\ high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD\ is high. Data at the parallel inputs are loaded directly into the register while SH/LD\ is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.