作为SpinalHDL语法篇的第一节,我们也从最简单的开始。
Bool类型定义
Bool类型就是Verilog中的单bit类型,定义方式如下:
Syntax | Description | Return |
---|---|---|
Bool() | 创建Bool类型变量 | Bool |
True | 创建Bool类型变量,并赋值true | Bool |
False | 创建Bool类型变量,并赋值false | Bool |
Bool(value: Boolean) | 创建Bool类型变量,并使用Scala表达式赋值 | Bool |
Example:
val a = Bool() val b = True val c = False val d = Bool( 1 > 2)
生成的Verilog代码如下:
wire a; wire b; wire c; wire d; assign b = 1'b1; assign c = 1'b0; assign d = 1'b0;
逻辑运算
下图为官方的逻辑运算解释,也不翻译了,很容易理解。
Operator | Description | Return type |
---|---|---|
!x | Logical NOT | Bool |
x && y | Logical And | Bool |
x & y | Logical And | Bool |
x || y | Logical OR | Bool |
x | y | Logical OR | Bool |
x ^ y | Logical XOR | Bool |
x.set[()] | Set x to True | Bool |
x.clear[()] | Set x to False | Bool |
x.setWhen(cond) | Set x when cond is True | Bool |
x.clearWhen(cond) | Clear x when cond is True | Bool |
x.riseWhen(cond) | Set x when x is False and cond is True | Bool |
x.fallWhen(cond) | Clear x when x is True and cond is True | Bool |
val e = a & b val f = a | b val g = a ^ b val h = !a val i = Bool() i.set() val j = Bool() j.clear() val k = True #这里必须有初值,否则下一句会报错 k.clearWhen(b) val l = True when(b){ l := False } val m = RegInit(False) #关于寄存器类型,这里先熟悉一下,后面章节会讲到 m.riseWhen(b)
边缘检测
Operator | Description | Return type |
---|---|---|
x.edge[()] | Return True when x changes state | Bool |
x.edge(initAt: bool) | Same as x.edge but with a reset value | Bool |
x.rise[()] | Return True when x was low at the last cycle and is now high | Bool |
x.rise(initAt: Bool) | Same as x.rise but with a reset value | Bool |
x.fall[()] | Return True when x was high at the last cycle and is now low | Bool |
x.fall(initAt: Bool) | Same as x.fall but with a reset value | Bool |
x.edges[()] | Return a bundle (rise, fall, toggle) | BoolEdges |
x.edges(initAt: Bool) | Same as x.edges but with a reset value | BoolEdges |
val a = Bool() val b = False when(a.edge()){ b := True } val c = a.edge(False)
转换后的代码为:
module DemoBool ( input clk, input reset ); wire a; reg b; reg a_regNext; wire when_DemoBool_l35; reg a_regNext_1; wire c; always @(*) begin b = 1'b0; if(when_DemoBool_l35) begin b = 1'b1; end end assign when_DemoBool_l35 = (a ^ a_regNext); assign c = (a ^ a_regNext_1); always @(posedge clk) begin a_regNext <= a; end always @(posedge clk or posedge reset) begin if(reset) begin a_regNext_1 <= 1'b0; end else begin a_regNext_1 <= a; end end endmodule
val edgeBundle = myBool_2.edges(False) when(edgeBundle.rise) { // do something when a rising edge is detected } when(edgeBundle.fall) { // do something when a falling edge is detected } when(edgeBundle.toggle) { // do something at each edge }
数值比对
Operator | Description | Return type |
---|---|---|
x === y | Equality | Bool |
x =/= y | Inequality | Bool |
审核编辑:汤梓红
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