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C8051微控制器IP软核的参数化设计
消耗积分:3 |
格式:rar |
大小:139 |
2009-07-30
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研究了C8051 微控制器IP 软核的参数化设计。首先介绍了指令系统的设计，其次从可重
配置的存储器容量、可取舍的并行输入/输出端口、是否产生UART 和定时/计数器模块，以及可重配置的乘法器等几个方面进行了参数化的设计，最后介绍了在不同功能参数配置下的仿真验证、综合结果及延时分析。参数化设计方法增强了IP 软核在SoC 应用中的可配置性和可重用性。
关键词：微控制器；软核；可配置性；可重用性
Abstract: The parameterized design about the C8051 micro controller IP soft core is studied. Firstly, he design of the instruction system is introduced. Secondly, from the reconfigurable capacitance of emory, parallel input/output port, UART and timer/counter which can be accepted or rejected, and he reconfigurable multiplier, the detailed method for the C8051 micro controller IP soft core about arameterized design is described. Finally, the verification of simulation, the result of synthesis and he delay analysis using different configurable parameters are introduced. The parameterized design ethod enhances the reconfigurable and reusable of IP soft core in the field of System on Chip design.
Key Words: micro controller; soft core; reconfigurable; reusable
配置的存储器容量、可取舍的并行输入/输出端口、是否产生UART 和定时/计数器模块，以及可重配置的乘法器等几个方面进行了参数化的设计，最后介绍了在不同功能参数配置下的仿真验证、综合结果及延时分析。参数化设计方法增强了IP 软核在SoC 应用中的可配置性和可重用性。
关键词：微控制器；软核；可配置性；可重用性
Abstract: The parameterized design about the C8051 micro controller IP soft core is studied. Firstly, he design of the instruction system is introduced. Secondly, from the reconfigurable capacitance of emory, parallel input/output port, UART and timer/counter which can be accepted or rejected, and he reconfigurable multiplier, the detailed method for the C8051 micro controller IP soft core about arameterized design is described. Finally, the verification of simulation, the result of synthesis and he delay analysis using different configurable parameters are introduced. The parameterized design ethod enhances the reconfigurable and reusable of IP soft core in the field of System on Chip design.
Key Words: micro controller; soft core; reconfigurable; reusable
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