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大型并行嵌入系统应用软件工程师的硬件设计模型

消耗积分:3 | 格式:rar | 大小:223 | 2009-11-30

孙成红

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Abstract Parallel servers are becoming an important sector in the embedded systems marketplace. If software engineers are to implement the multi-algorithm applications that these servers support, then educators should provide clear design routes which inculcate system-level thinking. Pipelined Processor Farms (PPF) is one such topdown design strategy. The contemporary hardware diversity within both processor- and instruction-level parallellism requires incorporation of a coprocessor model at the node or sub-system layer. Two suitable software-based approaches are reviewed: one which maintains the traditional aspects of hardware modeling, SystemC, and the other, Handel-C, which introduces silicon compilation to the CAD laboratory.
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