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DS34S101, DS34S102, DS34S104,
消耗积分:3 |
格式:rar |
大小:555 |
2008-08-10
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DS34S101, DS34S102, DS34S104, DS34S108
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3 or STS-1 stream
to be transported transparently over IP, MPLS or
Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standardsbased
TDM-over-packet mapping methods are
supported. Frame-based serial HDLC data flows are
also supported. The high level of integration available
with the DS34S10x devices minimizes cost, board
space, and time to market.
Single/Dual/Quad/Octal TDM-over-Packet Chip
General Description
These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC
compliant devices allow up to eight E1, T1 or serial
streams or one high-speed E3, T3 or STS-1 stream
to be transported transparently over IP, MPLS or
Ethernet networks. Jitter and wander of recovered
clocks conform to G.823/G.824, G.8261, and TDM
specifications. TDM data is transported in up to 64
individually configurable bundles. All standardsbased
TDM-over-packet mapping methods are
supported. Frame-based serial HDLC data flows are
also supported. The high level of integration available
with the DS34S10x devices minimizes cost, board
space, and time to market.
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