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MPEG-2 Video Decoding on the T
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2010-07-06
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Abstract
This paper explores implementation of MPEG-2 decoding
functions (bitstream parsing, IDCT, variable length
decoding, motion compensation, dequantization) in soft-
ware on the T.I. TMS320C6X architecture. We discuss
cycle count estimates for these functions; our estimates
are based on optimized, functionally accurate implementa-
tions in some cases, and on analysis of C implementations
of the function in other cases. We describe how we arrive
at these estimates in detail, and discuss how we were able
to use automatic compilation effectively for certain func-
tions. We also compare the C6x implementation to other
MPEG-2 implementations that have been reported for
general purpose CPUs that support a multimedia
enhanced instruction set, such as Intel Pentium (MMX),
SUN UltraSPARC (VIS), and HP PA (MAX).
This paper explores implementation of MPEG-2 decoding
functions (bitstream parsing, IDCT, variable length
decoding, motion compensation, dequantization) in soft-
ware on the T.I. TMS320C6X architecture. We discuss
cycle count estimates for these functions; our estimates
are based on optimized, functionally accurate implementa-
tions in some cases, and on analysis of C implementations
of the function in other cases. We describe how we arrive
at these estimates in detail, and discuss how we were able
to use automatic compilation effectively for certain func-
tions. We also compare the C6x implementation to other
MPEG-2 implementations that have been reported for
general purpose CPUs that support a multimedia
enhanced instruction set, such as Intel Pentium (MMX),
SUN UltraSPARC (VIS), and HP PA (MAX).
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