The X25642 is a CMOS 65,536-bit serial E 2 PROM, internally organized as 8K x 8. The X25642 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25642 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25642 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25642 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25642 utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.