资料下载
×
基于FPGA的差分信号阻抗匹配
消耗积分:5 |
格式:rar |
大小:652 |
2011-01-04
h1654155275.3301
分享资料个
为了节约PCB板空间，充分灵活利用FPGA内部资源，对FPGA内置差分信号匹配终端进行研究。根据差分信号阻抗匹配的基础理论，在自制的PCB电路板上利用差分信号线传递时钟和图像数据。在FPGA内设置不同类型的片内匹配终端，通过示波器观察时钟、图像数据，利用Visual DSP++软件自带的Image Viewer功能观察图像。结果表明，使用片内匹配终端不会恶化差分信号，并能大大节省PCB板空间，且终端匹配更灵活。
- Abstract:
- In order to save PCB board space，fully flexible use of FPGA internal resources，it did some research about the terminal in the FPGA which was used to match the differential signal.According to the basic theory about impedance match-ing of differential signal,the clock and image data by differential signal line in the self-made PCB circuit board was trans-mitted.The different OCT（on-chip termination）was set in FPGA，and the clock and image data signals through the oscillo-scope was observed the image by Image Viewer tool in Visual DSP++was also observed.The results show that the use of on-chip differential signal matched termination does not deteriorate dofferential signal,greatly reduces PCB board space，and makes the matching about terminal more flexible.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
