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DS90C387R,pdf datasheet (85MHz
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大小:551 |
2009-10-14
杨平
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The DS90C387R transmitter is designed to support pixel
data transmission from a Host to a Flat Panel Display up to
UXGA resolution. It is designed to be compatible with Graphics
Memory Controller Hub( GMCH) by implementing two
data per clock and can be controlled by a two-wire serial
communication interface. Two input modes are supported:
one port of 12-bit( two data per clock) input for 24-bit RGB,
and two ports of 12-bit( two data per clock) input for dual
24-bit RGB( 48-bit total). In both modes, input data will be
clocked on both rising and falling edges in LVTTL level
operation, or clocked on the cross over of differential clock
signals in the low swing operation. Each input data width will
be 1/2 of clock cycle. With an input clock at 85MHz and input
data at 170Mbps, the maximum transmission rate of each
LVDS line is 595Mbps, for a aggregate throughput rate of
2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual
Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential
Signaling) data streams. DS90C387R can be programmed
via the two-wire serial communication interface.
The LVDS output pin-out is identical to DS90C387. Thus,
this transmitter can be paired up with DS90CF388, receiver
of the 112MHz LDI chipset or FPD-Link Receivers in non-DC
Balance mode operation which provides GUI/LCD panel/
mother board vendors a wide choice of inter-operation with
LVDS based TFT panels.
data transmission from a Host to a Flat Panel Display up to
UXGA resolution. It is designed to be compatible with Graphics
Memory Controller Hub( GMCH) by implementing two
data per clock and can be controlled by a two-wire serial
communication interface. Two input modes are supported:
one port of 12-bit( two data per clock) input for 24-bit RGB,
and two ports of 12-bit( two data per clock) input for dual
24-bit RGB( 48-bit total). In both modes, input data will be
clocked on both rising and falling edges in LVTTL level
operation, or clocked on the cross over of differential clock
signals in the low swing operation. Each input data width will
be 1/2 of clock cycle. With an input clock at 85MHz and input
data at 170Mbps, the maximum transmission rate of each
LVDS line is 595Mbps, for a aggregate throughput rate of
2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual
Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential
Signaling) data streams. DS90C387R can be programmed
via the two-wire serial communication interface.
The LVDS output pin-out is identical to DS90C387. Thus,
this transmitter can be paired up with DS90CF388, receiver
of the 112MHz LDI chipset or FPD-Link Receivers in non-DC
Balance mode operation which provides GUI/LCD panel/
mother board vendors a wide choice of inter-operation with
LVDS based TFT panels.
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