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CADENCE SIP DIGITAL LAYOUT
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2008-10-16
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CADENCE SIP DIGITAL LAYOUT
While system-in-package (SiP) design allows electronics makers to pack more
functionality into a smaller footprint, it often involves highly complex combinations,
such as stacked wirebond die, wirebond die stacked on flip-chip die, direct die-to-
die attachment, and others. Cadence
SiP Digital Layout addresses this complexity
by providing a complete constraint- and rules-driven package substrate layout
environment that supports all packaging methods, including PGA, BGA, micro-BGA,
chip scale, as well as flip-chip and wirebond attach methods.
While system-in-package (SiP) design allows electronics makers to pack more
functionality into a smaller footprint, it often involves highly complex combinations,
such as stacked wirebond die, wirebond die stacked on flip-chip die, direct die-to-
die attachment, and others. Cadence
SiP Digital Layout addresses this complexity
by providing a complete constraint- and rules-driven package substrate layout
environment that supports all packaging methods, including PGA, BGA, micro-BGA,
chip scale, as well as flip-chip and wirebond attach methods.
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