资料下载
×
LAN9211 pdf datasheet (High-Pe
消耗积分:3 |
格式:rar |
大小:333 |
2008-12-26
分享资料个
The LAN9211 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded
applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9211 has been specifically designed to provide the highest performance possible for any 16-
bit application.The LAN9211 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and
supports HP Auto-MDIX.
The LAN9211 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave
interface. The simple, yet highly functional host bus interface provides a glue-less connection to most
common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit
external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit
checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The
LAN9211 also includes large transmit and receive data FIFOs to accommodate high latency
applications. In addition, the LAN9211 memory buffer architecture allows the most efficient use of
memory resources by optimizing packet granularity.
applications where performance, flexibility, ease of integration and system cost control are required.
The LAN9211 has been specifically designed to provide the highest performance possible for any 16-
bit application.The LAN9211 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and
supports HP Auto-MDIX.
The LAN9211 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave
interface. The simple, yet highly functional host bus interface provides a glue-less connection to most
common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit
external bus. The integrated checksum offload engines enable the automatic generation of the 16-bit
checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The
LAN9211 also includes large transmit and receive data FIFOs to accommodate high latency
applications. In addition, the LAN9211 memory buffer architecture allows the most efficient use of
memory resources by optimizing packet granularity.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
