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HM-6561 256 x 4 CMOS RAM
消耗积分:3 |
格式:rar |
大小:233 |
2009-01-09
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The HM-6561 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous circuit
design techniques are employed to achieve high performance
and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention supply
voltage and supply current are guaranteed over temperature.
using self-aligned silicon gate technology. Synchronous circuit
design techniques are employed to achieve high performance
and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention supply
voltage and supply current are guaranteed over temperature.
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