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MC9S12NE64,pdf(low-end connectivity applications MCU)
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2011-05-12
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The MC9S12NE64 is a 112-/80-pin cost-effective, low-end connectivity applications MCU family. TheMC9S12NE64 is composed of standard on-chip peripherals including a 16-bit central processing unit(HCS12 CPU), 64K bytes of FLASH EEPROM, 8K bytes of RAM, Ethernet media access controller(EMAC) with integrated 10/100 Mbps Ethernet physical transceiver (EPHY), two asynchronous serialcommunications interface modules (SCI), a serial peripheral interface (SPI), one inter-IC bus (IIC), a4-channel/16-bit timer module (TIM), an 8-channel/10-bit analog-to-digital converter (ATD), up to 21 pinsavailable as keypad wakeup inputs (KWU), and two additional external asynchronous interrupts. Theinclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operationalrequirements. Furthermore, an on-chip bandgap-based voltage regulator (VREG_PHY) generates theinternal digital supply voltage of 2.5 V (VDD) from a 3.15 V to 3.45 V external supply range. TheMC9S12NE64 has full 16-bit data paths throughout. The 112-pin package version has a total of 70 I/O portpins and 10 input-only pins available. The 80-pin package version has a total of 38 I/O port pins and 10input-only pins available.
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