资料下载
AT40K系列现场可编程门阵列设计软件发生器的介绍
分享资料个
The AT40K is comprised of a perfectly symmetrical array of octagonal
logic cells with direct connects to adjoining cells on all eight sides. The
number of connections between cells helps to conserve busing resources
and minimizes delays. More important, by providing diagonal connections
between cells, the chip allows the efficient implementation of extremely
high performance array multipliers as well as excellent support for synthesis-
based designs. The array also features five separate planes of high
speed busing, each of which contains one local bus and two ultra-fast
express buses. When combined with the extensive direct cell connections,
the busing network provide the FPGA with excellent routability.
The AT40K core cell includes two three-input LUTs, plus an upstream
AND gate. The two LUTs can be used to form a full-adder which, when
combined with the upstream AND gate, serves as a multiplier element.
Therefore, a multiplier of any size can be constructed using an array of
individual cells that are only directly connected.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
