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CD4094.pdf
消耗积分:10 |
格式:rar |
大小:122 |
2008-04-02
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The CD4094BC consists of an 8-bit shift register and a
3-STATE 8-bit latch. Data is shifted serially through the
shift register on the positive transition of the clock. The output
of the last stage (QS) can be used to cascade several
devices. Data on the QS output is transferred to a second
output, Q′S, on the following negative clock edge.
The output of each stage of the shift register feeds a latch,
which latches data on the negative edge of the STROBE
input. When STROBE is HIGH, data propagates through
the latch to 3-STATE output gates. These gates are
enabled when OUTPUT ENABLE is taken HIGH.
Features
Wide supply voltage range: 3.0V to 18V
High noise immunity: 0.45 VDD (typ.)
Low power TTL compatibility:
Fan out of 2 driving 74L
3-STATE 8-bit latch. Data is shifted serially through the
shift register on the positive transition of the clock. The output
of the last stage (QS) can be used to cascade several
devices. Data on the QS output is transferred to a second
output, Q′S, on the following negative clock edge.
The output of each stage of the shift register feeds a latch,
which latches data on the negative edge of the STROBE
input. When STROBE is HIGH, data propagates through
the latch to 3-STATE output gates. These gates are
enabled when OUTPUT ENABLE is taken HIGH.
Features
Wide supply voltage range: 3.0V to 18V
High noise immunity: 0.45 VDD (typ.)
Low power TTL compatibility:
Fan out of 2 driving 74L
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