资料下载
×
SCN68 26562(NDUSCC)和SC68 26C56
消耗积分:2 |
格式:rar |
大小:68 |
2009-06-18
分享资料个
Refer to the Transmitter data path in the data sheet. The status bit
TRSR[7] is set when the Tx shift register is empty and no other
characters (from the TxFlFO special char. or Sync char.) are waiting
to fill it. There can be a one bit time delay due to the Data Encoder
after the Tx SR is empty and before the last bit of the character is
seen on the TxD pin. The TEOM command causes the FCS to be
sent after the next character put into the Tx FIFO is sent. The CRC
generation takes place after the Tx SR, so TRSR[7] will be set after
the FlFOed character is serialized but before FCS is sent. Another
status bit, Frame Complete, TRSR[5] is set when transmission of
the FCS begins.
TRSR[7] is set when the Tx shift register is empty and no other
characters (from the TxFlFO special char. or Sync char.) are waiting
to fill it. There can be a one bit time delay due to the Data Encoder
after the Tx SR is empty and before the last bit of the character is
seen on the TxD pin. The TEOM command causes the FCS to be
sent after the next character put into the Tx FIFO is sent. The CRC
generation takes place after the Tx SR, so TRSR[7] will be set after
the FlFOed character is serialized but before FCS is sent. Another
status bit, Frame Complete, TRSR[5] is set when transmission of
the FCS begins.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
评论(0)
发评论
- 相关下载
- 相关文章
