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74HC112引脚及功能介绍

消耗积分:0 | 格式:pdf | 大小:126KB | 2014-08-26

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These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits， along with the ability to drive 10
LS-TTL loads. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs and Q and Q outputs。 These devices are edge sensitive to the clock input and change state on the negative going transition of the clock pulse。Clear and pre-set are independent of the clock and accomplished by a low logic level on the corresponding input。The 54HC/74HC logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family。All inputs are protected from damage due to static dis-charge by internal diode clamps to VCC and ground。
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