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STM8L051F3 STM8L151x2/x3 Errata

消耗积分:1 | 格式:pdf | 大小:321KB | 2017-03-07

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STM8L051F3 STM8L151x2/x3 Errata sheet STM8L051F3, STM8L151x2 and STM8L151x3 revision Z device limitations

　　Core limitations 1.1.1 Interrupt service routine （ISR） executed with priority of main process Description If an interrupt is cleared or masked when the context saving has already started， the corresponding ISR is executed with the priority of the main process. Workaround None. No fix is planned for this limitation. 1.1.2 Main CPU execution is not resumed after an ISR resets the AL bit Description If the CPU is in wait for interrupt state and the AL bit is set， the CPU returns to wait for interrupt state after executing an ISR. To continue executing the main program， the AL bit must be reset by the ISR. When AL is reset just before exiting the ISR， the CPU may remain stalled. Workaround Reset the AL bit at least two instructions before the IRET instruction. No fix is planned for this limitation.

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