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DS99R421,pdf datasheet (5-43 M
消耗积分:2 |
格式:rar |
大小:558 |
2009-10-14
鼠爱米
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The DS99R421 converts a FPD-Link input with 4 non-DC
Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled
low speed control bits into a single LVDS DC-balanced
serial stream with embedded clock information. This
single serial stream simplifies transferring the 24-bit bus over
a single differential pair of PCB traces and cable by eliminating
the skew problems between the 3 parallel LVDS data
inputs and LVDS clock paths. It saves system cost by narrowing
4 LVDS pairs to 1 LVDS pair that in turn reduce PCB
layers, cable width, connector size, and pins.
Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 oversampled
low speed control bits into a single LVDS DC-balanced
serial stream with embedded clock information. This
single serial stream simplifies transferring the 24-bit bus over
a single differential pair of PCB traces and cable by eliminating
the skew problems between the 3 parallel LVDS data
inputs and LVDS clock paths. It saves system cost by narrowing
4 LVDS pairs to 1 LVDS pair that in turn reduce PCB
layers, cable width, connector size, and pins.
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