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71m65xxSPI接口
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In order to avoid access conflicts and to ensure data integrity， the following procedure must be used when accessing I/O RAM registers： 1） The SPI host should send a command with the command word 100x xxxx or 110x xxxx before the actual read or write command. 2） The SPI slave interface will load the command register and generate an INT2 interrupt upon receiving the command. 3） The MPU should service the interrupt and halt any external data memory operations to effectively grant the bus to the SPI. 4） When the SPI host finishes its I/O RAM access， it should send another command so the MPU can release the bus. There are no issues with Data RAM access; SPI and the MPU will share the bus with no conflicts for Data RAM access.
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