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TI_XIO1100NAND的树测试以太网交换机
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The common method for checking the interconnections between the ICs is to use JTAG
boundary scan. Since the XIO1100 PHY does not support JTAG boundary scan， a NAND-tree
feature has to be employed.
A NAND tree is exactly how it sounds： A number of nested NAND gates in which each I/O pin is
an input to one NAND gate. Figure 1 illustrates a NAND tree. The output of the nested NAND
gates is provided on the JTAG_TDO pin. A NAND-tree feature does not provide 100% coverage
but does allow for checking the connectivity of most I/Os on the XIO1100 PHY.
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