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74HC620/74HC623 pdf datasheet
消耗积分:5 |
格式:rar |
大小:133 |
2008-08-06
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The M54/74HC620/623 are high speed CMOS
OCTAL BUS TRANSCEIVERS fabricated in silicon
gate C2MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
These octal bus transceivers are designed for asynchronous
two-way communication between data
buses. The control function implementation allows
maximum flexibility in timing.
These devices allow data transmission from the A
bus to B bus or from the B to the A bus depending
upon the logic levels at the enable inputs (GBAand
GAB). The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these devices
the capability to storedata by simultaneous enabling
of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus
lines (16 in all) will remain at their last states. The 8-
bit codes appearing on the two sets of buses will be
identical for the ’HC623 or complementary for the
’HC620. All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
OCTAL BUS TRANSCEIVERS fabricated in silicon
gate C2MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power consumption.
These octal bus transceivers are designed for asynchronous
two-way communication between data
buses. The control function implementation allows
maximum flexibility in timing.
These devices allow data transmission from the A
bus to B bus or from the B to the A bus depending
upon the logic levels at the enable inputs (GBAand
GAB). The enable inputs can be used to disable the
device so that the buses are effectively isolated.
The dual-enable configuration gives these devices
the capability to storedata by simultaneous enabling
of GBA and GAB.
Each output reinforces its input in this transceiver
configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus
lines (16 in all) will remain at their last states. The 8-
bit codes appearing on the two sets of buses will be
identical for the ’HC623 or complementary for the
’HC620. All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
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