VHDL源代码

VHDL源代码：
 library ieee;                      --显示器彩条发生器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity VGA is
   port(clk,mode   :in std_logic;    --扫描时钟/显示模式选择时钟
        d,hs,vs,r,g,b:out std_logic);  --行，场同步/红，绿，蓝
end VGA;

architecture a of VGA is
    signal hs1,vs1,fclk,cclk,divide_clk,dly:  std_logic;
    signal mmode :std_logic_vector(1 downto 0);     --方式选择
    signal cnt :std_logic_vector(2 downto 0);
    signal fs :std_logic_vector(3 downto 0);
    signal cc :std_logic_vector(4 downto 0);        --行同步/横彩条生成
    signal ll :std_logic_vector(8 downto 0);        --长同步/竖彩条生成
    signal grbh :std_logic_vector(3 downto 1);      --X 横彩条
    signal grby :std_logic_vector(3 downto 1);      --Y 竖彩条
    signal grbx :std_logic_vector(3 downto 1);      --文字
    signal grbt :std_logic_vector(3 downto 1);      --图案
    signal grbp :std_logic_vector(3 downto 1);     
    signal grb  :std_logic_vector(3 downto 1);
    signal x :integer range 0 to 800;
    signal x1: integer range 0 to 800;
    signal y1: integer range 0 to 600;
    signal x2: integer range 0 to 800;
    signal x3: integer range 0 to 800;
    signal x4: integer range 0 to 800;
    signal x5: integer range 0 to 800;
    signal x7: integer range 0 to 800;
    signal x8: integer range 0 to 800;
    signal x9: integer range 0 to 800;
    signal x10: integer range 0 to 800;
    signal x11: integer range 0 to 800;

    signal y2: integer range 0 to 600;
    signal y3: integer range 0 to 600;
    signal y4: integer range 0 to 600;
    signal y5: integer range 0 to 600;
    signal y6: integer range 0 to 600;
    signal c: integer range 0 to 30;