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PTN products demo board docume
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2009-03-29
王银喜
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The PTN Demo Board utilizes the following products: PTN1111– a
1:10 PECL Clock distributing device, PTN3311– a PECL to LVDS
translator, a PTN2111– a 1:10 LVDS Clock Distributing device,
PTN3310– a LVDS to PECL translator, and PTN3322– a universal
translator. For more information on the PTN products themselves,
please, refer to their corresponding data sheets.
The purpose of the Demo Board is to show the simultaneous
operation of all of the above devices, and it is the main mode of
operation for the board. However, the board also allows for
independent operation for some of the products.
In the main mode of operation, the PTN1111 gets its input signal
from a pattern generator via the SMA J6 & SMA J8. One of the
PTN1111 outputs goes into the receiver of PTN3311. The output of
PTN3311 feds into one of the clock inputs of PTN2111 if and only if
resistors R23 and R24 are assembled. Then, one of the outputs of
PTN2111 is fed into the input of the PTN3310, and its outputs are
connected to SMA J45 & J7, which could be fed into an
oscilloscope. The original signal of this loop is PECL, and the final
output signal is also PECL after it has been translated to and then
again from LVDS.
The PTN3322 could provide an input to either the PTN1111 or the
PTN2111, as selected by the L/P pin of Switch 1. If the PTN3322 is
to drive the PTN1111, resistors R13 and R14 must be soldered to
the board, and then the PTN3322 becomes the default source of the
main loop. The PTN1111’s clock select pin, Clk_Sel, on Switch 2
must be in open position. Alternatively, if the PTN3322 is to be a
signaling source for the PTN2111, the Si pin of Switch 1 must be in
an open position.
1:10 PECL Clock distributing device, PTN3311– a PECL to LVDS
translator, a PTN2111– a 1:10 LVDS Clock Distributing device,
PTN3310– a LVDS to PECL translator, and PTN3322– a universal
translator. For more information on the PTN products themselves,
please, refer to their corresponding data sheets.
The purpose of the Demo Board is to show the simultaneous
operation of all of the above devices, and it is the main mode of
operation for the board. However, the board also allows for
independent operation for some of the products.
In the main mode of operation, the PTN1111 gets its input signal
from a pattern generator via the SMA J6 & SMA J8. One of the
PTN1111 outputs goes into the receiver of PTN3311. The output of
PTN3311 feds into one of the clock inputs of PTN2111 if and only if
resistors R23 and R24 are assembled. Then, one of the outputs of
PTN2111 is fed into the input of the PTN3310, and its outputs are
connected to SMA J45 & J7, which could be fed into an
oscilloscope. The original signal of this loop is PECL, and the final
output signal is also PECL after it has been translated to and then
again from LVDS.
The PTN3322 could provide an input to either the PTN1111 or the
PTN2111, as selected by the L/P pin of Switch 1. If the PTN3322 is
to drive the PTN1111, resistors R13 and R14 must be soldered to
the board, and then the PTN3322 becomes the default source of the
main loop. The PTN1111’s clock select pin, Clk_Sel, on Switch 2
must be in open position. Alternatively, if the PTN3322 is to be a
signaling source for the PTN2111, the Si pin of Switch 1 must be in
an open position.
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