资料下载
32K×8位低功耗CMOS SRAM,AS6C62256A
分享资料个
The AS6C62256A is a static RAM manufactured using a CMOS process technology with the following operating modes： - Read - Standby - Write - Data Retention The memory array is based on a 6- transistor cell. The circuit is activated by the falling edge of E. The address and control inputs open simultaneously. According to the information of W and G， the data inputs， or outputs， are active. In a Read cycle， the data outputs are activated by the falling edge of G， afterwards the data word read will be available at the outputs DQ0-DQ7. After the address change， the data outputs go High-Z until the new information read is available. The data outputs have not preferred state. The Read cycle is finished by the falling edge of W， or by the rising edge of E， respectively. Data retention is guaranteed down to 2 V. With the exception of E， all inputs consist of NOR gates， so that no pull-up/pull-down resistors are required.
声明：本文内容及配图由入驻作者撰写或者入驻合作网站授权转载。文章观点仅代表作者本人，不代表电子发烧友网立场。文章及其配图仅供工程师学习之用，如有内容侵权或者其他违规问题，请联系本站处理。 举报投诉
- 相关下载
- 相关文章
