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CADENCE SIP RF LAYOUT
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2008-10-16
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CADENCE SIP RF LAYOUT
While system-in-package (SiP) design makes it possible to combine RF and analog
content on the same substrate, it presents a number of challenges. These include
designing and integrating RF/analog chips with substrate-level buried RF passive
devices as well as enabling top-level pre- and post-layout circuit simulation of
the entire SiP design. Cadence
SiP RF Layout provides the proven path between
Virtuoso
analog design/simulation and substrate layout. It enables layout
designers to implement a SiP RF design that includes RF/analog die, embedded
RF discretes, constraint-driven interconnect routing, and full SiP tapeout
manufacturing preparation.
While system-in-package (SiP) design makes it possible to combine RF and analog
content on the same substrate, it presents a number of challenges. These include
designing and integrating RF/analog chips with substrate-level buried RF passive
devices as well as enabling top-level pre- and post-layout circuit simulation of
the entire SiP design. Cadence
SiP RF Layout provides the proven path between
Virtuoso
analog design/simulation and substrate layout. It enables layout
designers to implement a SiP RF design that includes RF/analog die, embedded
RF discretes, constraint-driven interconnect routing, and full SiP tapeout
manufacturing preparation.
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