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RT9644/RT9644A pdf datasheet (
消耗积分:3 |
格式:rar |
大小:361 |
2008-12-14
h1654155957.9921
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The RT9644/A is a complete ACPI compliant power
solution for DDR and DDR2 memory system with up to 4
DIMMs dual channel systems. This RT9644 includes one
synchronous buck controller for DDR/DDR2 VDDQ, one
DDR/DDR2 bus terminator VTT (equal to VDDQ/2) regulator
with source and sinking ability, three LDO controllers for
VGMCH (cascode), and GMCH/CPU termination
VTT_GMCH/CPU. The RT9644A includes one synchronous
buck controller for DDR/DDR2 VDDQ, one PWM controller
for VGMCH (with external MOSFET driver), one DDR/DDR2
bus terminator VTT (equal to VDDQ/2) regulator with source
and sinking ability, and two LDO controllers for
VTT_GMCH/CPU and VDAC.
These parts also provide a reference buffer for DDR/DDR2
input reference voltage generator. When during S0 state,
the VIDPGD indicates the GMCH_CPU VTT within spec
and operational. The synchronous buck DC-DC PWM is
implemented by two N-MOSFETs as upper and lower
MOSFETs with voltage mode control. The linear controllers
are implemented with one N-MOSFET with suitable
capacitance. Each output is monitored by under voltage
protection (RT9644 except VGMCHH and RT9644A except
VDAC). VDDQ PWM controller and DDR/DDR2 bus
terminator regulator have over voltage protection. Moreover,
the VDDQ PWM controller has the over current protection
by external resister adjustment. Thermal shut down is
integrated. All the internal voltage reference is fixed at
0.8V, and users can adjust the resistance divider for desired
voltage output.
solution for DDR and DDR2 memory system with up to 4
DIMMs dual channel systems. This RT9644 includes one
synchronous buck controller for DDR/DDR2 VDDQ, one
DDR/DDR2 bus terminator VTT (equal to VDDQ/2) regulator
with source and sinking ability, three LDO controllers for
VGMCH (cascode), and GMCH/CPU termination
VTT_GMCH/CPU. The RT9644A includes one synchronous
buck controller for DDR/DDR2 VDDQ, one PWM controller
for VGMCH (with external MOSFET driver), one DDR/DDR2
bus terminator VTT (equal to VDDQ/2) regulator with source
and sinking ability, and two LDO controllers for
VTT_GMCH/CPU and VDAC.
These parts also provide a reference buffer for DDR/DDR2
input reference voltage generator. When during S0 state,
the VIDPGD indicates the GMCH_CPU VTT within spec
and operational. The synchronous buck DC-DC PWM is
implemented by two N-MOSFETs as upper and lower
MOSFETs with voltage mode control. The linear controllers
are implemented with one N-MOSFET with suitable
capacitance. Each output is monitored by under voltage
protection (RT9644 except VGMCHH and RT9644A except
VDAC). VDDQ PWM controller and DDR/DDR2 bus
terminator regulator have over voltage protection. Moreover,
the VDDQ PWM controller has the over current protection
by external resister adjustment. Thermal shut down is
integrated. All the internal voltage reference is fixed at
0.8V, and users can adjust the resistance divider for desired
voltage output.
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