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HSP43883 pdf datasheet (Decima
消耗积分:5 |
格式:rar |
大小:3354 |
2009-01-06
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The HSP43220/883 Decimating Digital Filter is a linear
phase low pass decimation filter which is optimized for
filtering narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220/883 offers a single
chip solution to signal processing application which have
historically required several boards of ICs. This reduction in
component count results in faster development times, as
well as reduction of hardware costs.
The HSP43220/883 is implemented as a two stage filter
structure. As seen in the Block Diagram, the first stage is a
High Order Decimation Filter (HDF) which utilizes an
efficient decimation (sample rate reduction) technique to
obtain decimation up to 1024 through a coarse low-pass
filtering process. The HDF provides up to 96dB aliasing
rejection in the signal pass band. The second stage consists
of a Finite Impulse Response (FIR) decimation filter
structured as a transversal FIR filter with up to 512
symmetric taps which can implement filters with sharp
transition regions. The FIR can perform further decimation
by up to 16 if required, while preserving the 96dB aliasing
attenuation obtained by the HDF. The combined total
decimation capability is 16,384.
The HSP43220/883 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 30MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220/883 also provides the capability to bypass either
the HDF or the FIR for additional flexibility.
phase low pass decimation filter which is optimized for
filtering narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220/883 offers a single
chip solution to signal processing application which have
historically required several boards of ICs. This reduction in
component count results in faster development times, as
well as reduction of hardware costs.
The HSP43220/883 is implemented as a two stage filter
structure. As seen in the Block Diagram, the first stage is a
High Order Decimation Filter (HDF) which utilizes an
efficient decimation (sample rate reduction) technique to
obtain decimation up to 1024 through a coarse low-pass
filtering process. The HDF provides up to 96dB aliasing
rejection in the signal pass band. The second stage consists
of a Finite Impulse Response (FIR) decimation filter
structured as a transversal FIR filter with up to 512
symmetric taps which can implement filters with sharp
transition regions. The FIR can perform further decimation
by up to 16 if required, while preserving the 96dB aliasing
attenuation obtained by the HDF. The combined total
decimation capability is 16,384.
The HSP43220/883 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 30MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220/883 also provides the capability to bypass either
the HDF or the FIR for additional flexibility.
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