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HSP45883 pdf datasheet(Numeric
消耗积分:3 |
格式:rar |
大小:333 |
2009-01-06
刘高
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The Intersil HSP45116/883 combines a high performance
quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As shown
in the Block Diagram, the HSP45116/883 is divided into three
main sections. The Phase/Frequency Control Section (PFCS)
and the Sine/Cosine Section together form a complex NCO.
The CMAC multiplies the output of the Sine/Cosine Section
with an external complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.006Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC multiplies
this (cos, sin) vector by an external complex vector and
can accumulate the result. The resulting complex vectors are
available through two 20-bit output ports which maintain the
90dB spectral purity. This result can be accumulated internally
to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
quadrature numerically controlled oscillator (NCO) and a high
speed 16-bit Complex Multiplier/Accumulator (CMAC) on a
single IC. This combination of functions allows a complex
vector to be multiplied by the internally generated (cos, sin)
vector for quadrature modulation and demodulation. As shown
in the Block Diagram, the HSP45116/883 is divided into three
main sections. The Phase/Frequency Control Section (PFCS)
and the Sine/Cosine Section together form a complex NCO.
The CMAC multiplies the output of the Sine/Cosine Section
with an external complex vector.
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The phase resolution of the PFCS is 32 bits, which results in
frequency resolution better than 0.006Hz at 25.6MHz. The
output of the PFCS is the argument of the sine and cosine.
The spurious free dynamic range of the complex sinusoid is
greater than 90dBc.
The output vector from the Sine/Cosine Section is one of the
inputs to the Complex Multiplier/Accumulator. The CMAC multiplies
this (cos, sin) vector by an external complex vector and
can accumulate the result. The resulting complex vectors are
available through two 20-bit output ports which maintain the
90dB spectral purity. This result can be accumulated internally
to implement an accumulate and dump filter.
A quadrature down converter can be implemented by
loading a center frequency into the Phase/Frequency
Control Section. The signal to be downconverted is the
Vector Input of the CMAC, which multiplies the data by the
rotating vector from the Sine/Cosine Section. The resulting
complex output is the down converted signal.
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