• AD5757

• EVAL-AD5757SDZ

This lab presents the steps to setup an environment for using the EVAL-AD5757SDZ evaluation board together with the BeMicro SDK USB stick, the Nios II Embedded Development Suite (EDS) and the Micrium μC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-AD5757SDZ Evaluation Board with the BeMicro SDK Platform.

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5757SDZ Evaluation Board.

The AD5757 is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulat-ing the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5757.

The EVAL-AD5757SDZ evaluation board is designed to help customers quickly prototype new AD5757 circuits and reduce design time. To power the AD5757SDZ evaluation board supply 15V between the AVSS (0V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage.

• AD5757 Product Info - pricing, samples, datasheet
• EVAL-AD5757SDZ evaluation board user guide
• BeMicro SDK
• Nios II Embedded Development Suite (EDS)
• Micrium uC-Probe

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Below is presented the list of required hardware items:

• Arrow Electronics BeMicro SDK FPGA-based MCU Evaluation Board
• BeMicro SDK/SDP Interposer adapter board
• EVAL-AD5757SDZ evaluation board
• Intel Pentium III or compatible Windows PC, running at 866MHz or faster, with a minimum of 512MB of system memory

Below is presented the list of required software tools:

• Quartus II Web Edition design software v11.0
• Nios II EDS v11.0
• uC-Probe run-time monitoring tool, version 2.5

The Quartus II design software and the Nios II EDS is available via the Altera Complete Design Suite DVD or by downloading from the web.

The Micrium uC/Probe Trial version 2.5 is available via download from the web at http://micrium.com/tools/ucprobe/trial/. After installation add to the “Path” system variable the entry “%QUARTUS_ROOTDIR%/bin/“ on the third position in the list.

• Lab Design Files

Create a folder called “ADIEvalBoardLab” on your PC and extract the ad5757_evalboardlab.zip archive to this folder. Make sure that there are NO SPACES in the directory path. After extracting the archive the following folders should be present in the ADIEvalBoardLab folder: FPGA, Software, ucProbeInterface, NiosCpu.

A notable challenge in embedded systems development is to overcome the lack of feedback that such systems typically provide. Many developers resort to blinking LEDs or instrumenting their code with printf() in order to determine whether or not their systems are running as expected. Micrium provides a unique tool named μC-Probe to assist these developers. With this tool, developers can effortlessly read and write the variables on a running embedded system. This section presents the steps required to install the Micrium uC-Probe software tool and to run the demonstration project for the ADI evaluation board. A description of the uC-Probe demonstration interface is provided.

Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.

Select uC-Probe options.

• Click on the uC-Probe icon on the top left portion of the screen.
• Click on the Options button to open the dialog box.

Set target board communication protocol as JTAG UART

• Click on the Communication tab icon on the top left portion of the dialog box
• Select the JTAG UART option.

Setup JTAG UART communication settings

• Select the JTAG-UART option from the Communication tab.
• Press the Open File button to select the JTAG Debug Information file (.jdi)
• Navigate to the ADIEvalBoardLab/FPGA folder and select the BeMicroSDK.jdi file. Press Open.
• Type the value 1 in the the Device Id window.

• Select uCProbe_uart(0) from the Instance Id pulldown menu.

• Press Apply and OK to exit the options menu. The embedded target has two UARTs. uC-Probe will be communicating with the uCProbe_uart.

• Click the Open option from the uC-Probe menu and select the file ADIEvalBoardLab/ucProbeInterface/AD5757_Interface.wsp.

• Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. If the lab was done according to the steps provided in the Quick Evaluation section, select the file ADIEvalBoardLab/ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file, otherwise select the file ADIEvalBoardLab/FPGA/software/ADIEvalBoard/ADIEvalBoard.elf to be loaded as a symbol file.

• Run the demonstration project by pressing the Play button.

The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-AD5757SDZ evaluation board.

Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board.

Section B is used to select the DAC channel.

Section C is used to write data into the register selected by the Selection Slider.

Options:

• Write to DAC data register (individual channel write).
• Write to gain register (individual channel write).
• Write to gain register (all DACs).
• Write to offset register (individual channel write).
• Write to offset register (all DACs) .
• Write to clear code register (individual channel write).

Section D is used to read data from the register selected by the Selection Slider.

Options:

• Read from DAC data register (individual channel read).
• Read from DAC control register (individual channel read).
• Read from Gain register (individual channel read).
• Read from Offset register (individual channel read).
• Read from Clear Code register (individual channel read).
• Read from Slew Rate control register (individual channel read).
• Read from Status register.
• Read from Main control register.
• Read from DC-to-DC control register.

Section E is used to write data into the DAC n Control Register.

Options:

• Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel.
• Clear – Clear enable bit.
• Output – Enables/disables the selected output channel.
• Rset – Selects an internal or external current sense resistor for the selected DAC channel.
• DC-DC – Powers the dc-to-dc converter on the selected channel.
• Output Range – Selects the output range to be enabled.

Section F is used to write data into the DC-DC Control Register.

Options:

• DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter.
• Phase – User programmable dc-to-dc converter phase (between channels).
• Frequency – DC-to-dc switching frequency.
• Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter.

Section G is used to write data into the Main Control Register.

Options:

• StartRead – Enable status readback during a write.
• EWD – Enable watchdog timer.
• WD Period – Select the timeout period for the watchdog timer.
• OutEn All – Enables the output on all four DACs simultaneously.
• DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously.

Section H is used to write data into the Slew Rate Control Register.

Options:

• SE – Enable SE.
• SR Clock – Slew Rate Update Clock Options.
• SR Step – Slew Rate Step Size Options.

Section I is used to write data into the Software Register.

Options:

• User Bit – This bit is mapped to Bit D11 of the status register.
• Software Reset – Performs a reset of the AD5757.