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MAXQ1850 pdf datasheet (Secure
消耗积分:10 |
格式:rar |
大小:333 |
2009-02-15
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The MAXQ1850 is a low-power, 32-bit RISC device designed for electronic commerce, banking, and data security systems. It combines high-performance, single-cycle processing, sophisticated tamper-detection technology, and advanced cryptographic hardware to provide industry-leading data security and secret key protection.
Physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with an instantaneous zeroization of critical data. Four self-destruct inputs are provided for additional tamper response. An internal shield over the silicon provides protection from microprobe attacks. A high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. To protect data, the MAXQ1850 integrates several high-speed, analysis-resistant encryption engines. Algorithms supported in hardware include AES (128-, 192-, and 256-bit), DES, triple DES (2-key and 3-key), ECDSA (160-, 192-, and 256-bit keys), DSA, RSA (up to 2048 bits), SHA-1, SHA-224, and SHA-256. The advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria certifications.
The MAXQ1850 includes 256KB of flash memory and 8KB of secure, battery-backed data SRAM. Several communication protocols are supported with hardware engines, including ISO 7816 for smart card applications, USB (slave interface with four end-point buffers), an RS-232 UART, an SPI™ interface (master or slave mode support), and up to 16 general-purpose I/O pins. Other peripherals supported on the MAXQ1850 include a true hardware random-number generator (RNG), a real-time clock (RTC), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (PWM) operations.
Physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with an instantaneous zeroization of critical data. Four self-destruct inputs are provided for additional tamper response. An internal shield over the silicon provides protection from microprobe attacks. A high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. To protect data, the MAXQ1850 integrates several high-speed, analysis-resistant encryption engines. Algorithms supported in hardware include AES (128-, 192-, and 256-bit), DES, triple DES (2-key and 3-key), ECDSA (160-, 192-, and 256-bit keys), DSA, RSA (up to 2048 bits), SHA-1, SHA-224, and SHA-256. The advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria certifications.
The MAXQ1850 includes 256KB of flash memory and 8KB of secure, battery-backed data SRAM. Several communication protocols are supported with hardware engines, including ISO 7816 for smart card applications, USB (slave interface with four end-point buffers), an RS-232 UART, an SPI™ interface (master or slave mode support), and up to 16 general-purpose I/O pins. Other peripherals supported on the MAXQ1850 include a true hardware random-number generator (RNG), a real-time clock (RTC), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (PWM) operations.
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